diff options
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll b/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll index 889a5372991..9e276cdfbf1 100644 --- a/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll +++ b/llvm/test/CodeGen/AArch64/fp16_intrinsic_lane.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s +declare half @llvm.aarch64.neon.fmulx.f16(half, half) declare <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half>, <4 x half>) declare <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half>, <8 x half>) declare <4 x half> @llvm.fma.v4f16(<4 x half>, <4 x half>, <4 x half>) @@ -236,6 +237,25 @@ entry: ret half %1 } +define dso_local half @t_vmulx_f16(half %a, half %b) { +; CHECK-LABEL: t_vmulx_f16: +; CHECK: fmulx h0, h0, h1 +; CHECK-NEXT: ret +entry: + %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b) + ret half %fmulx.i +} + +define dso_local half @t_vmulxh_lane_f16(half %a, <4 x half> %b, i32 %lane) { +; CHECK-LABEL: t_vmulxh_lane_f16: +; CHECK: fmulx h0, h0, v1.h[3] +; CHECK-NEXT: ret +entry: + %extract = extractelement <4 x half> %b, i32 3 + %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract) + ret half %fmulx.i +} + define dso_local <4 x half> @t_vmulx_lane_f16(<4 x half> %a, <4 x half> %b, i32 %lane) { ; CHECK-LABEL: t_vmulx_lane_f16: ; CHECK: fmulx v0.4h, v0.4h, v1.h[0] @@ -276,6 +296,16 @@ entry: ret <8 x half> %vmulx2.i } +define dso_local half @t_vmulxh_laneq_f16(half %a, <8 x half> %b, i32 %lane) { +; CHECK-LABEL: t_vmulxh_laneq_f16: +; CHECK: fmulx h0, h0, v1.h[7] +; CHECK-NEXT: ret +entry: + %extract = extractelement <8 x half> %b, i32 7 + %fmulx.i = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %extract) + ret half %fmulx.i +} + define dso_local <4 x half> @t_vmulx_n_f16(<4 x half> %a, half %c) { ; CHECK-LABEL: t_vmulx_n_f16: ; CHECK: dup v1.4h, v1.h[0] |
