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-rw-r--r--llvm/include/llvm/IR/IntrinsicsAArch64.td13
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.cpp4
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.h1
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td24
-rw-r--r--llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll42
5 files changed, 73 insertions, 11 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index a3827aa3342..a7fa58331ea 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -923,6 +923,11 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
LLVMVectorElementType<0>],
[IntrNoMem]>;
+ class AdvSIMD_SVE_PTRUE_Intrinsic
+ : Intrinsic<[llvm_anyvector_ty],
+ [llvm_i32_ty],
+ [IntrNoMem, ImmArg<0>]>;
+
class AdvSIMD_SVE_PUNPKHI_Intrinsic
: Intrinsic<[LLVMHalfElementsVectorType<0>],
[llvm_anyvector_ty],
@@ -951,7 +956,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
class AdvSIMD_SVE_CNTB_Intrinsic
: Intrinsic<[llvm_i64_ty],
[llvm_i32_ty],
- [IntrNoMem]>;
+ [IntrNoMem, ImmArg<0>]>;
class AdvSIMD_SVE_CNTP_Intrinsic
: Intrinsic<[llvm_i64_ty],
@@ -1427,6 +1432,12 @@ def int_aarch64_sve_ucvtf_f32i64 : Builtin_SVCVT<"svcvt_f32_u64_m", llvm_nxv4
def int_aarch64_sve_ucvtf_f64i32 : Builtin_SVCVT<"svcvt_f64_u32_m", llvm_nxv2f64_ty, llvm_nxv4i32_ty>;
//
+// Predicate creation
+//
+
+def int_aarch64_sve_ptrue : AdvSIMD_SVE_PTRUE_Intrinsic;
+
+//
// Predicate operations
//
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 87a320dfd3a..85bbb3fc43c 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1347,6 +1347,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
case AArch64ISD::UUNPKHI: return "AArch64ISD::UUNPKHI";
case AArch64ISD::UUNPKLO: return "AArch64ISD::UUNPKLO";
case AArch64ISD::INSR: return "AArch64ISD::INSR";
+ case AArch64ISD::PTRUE: return "AArch64ISD::PTRUE";
case AArch64ISD::GLD1: return "AArch64ISD::GLD1";
case AArch64ISD::GLD1_SCALED: return "AArch64ISD::GLD1_SCALED";
case AArch64ISD::GLD1_SXTW: return "AArch64ISD::GLD1_SXTW";
@@ -2921,6 +2922,9 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::aarch64_sve_uunpklo:
return DAG.getNode(AArch64ISD::UUNPKLO, dl, Op.getValueType(),
Op.getOperand(1));
+ case Intrinsic::aarch64_sve_ptrue:
+ return DAG.getNode(AArch64ISD::PTRUE, dl, Op.getValueType(),
+ Op.getOperand(1));
case Intrinsic::aarch64_sve_insr: {
SDValue Scalar = Op.getOperand(2);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index fee8d21c2a6..1ee134c5bfc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -205,6 +205,7 @@ enum NodeType : unsigned {
UUNPKLO,
INSR,
+ PTRUE,
// Unsigned gather loads.
GLD1,
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 244397cbc37..99070b21480 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -18,7 +18,7 @@ def SVEPatternOperand : AsmOperandClass {
let DiagnosticType = "InvalidSVEPattern";
}
-def sve_pred_enum : Operand<i32>, ImmLeaf<i32, [{
+def sve_pred_enum : Operand<i32>, TImmLeaf<i32, [{
return (((uint32_t)Imm) < 32);
}]> {
@@ -249,11 +249,12 @@ def sve_incdec_imm : Operand<i32>, ImmLeaf<i32, [{
// it's important we define them first.
//===----------------------------------------------------------------------===//
-class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
+class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
+ ValueType vt, SDPatternOperator op>
: I<(outs pprty:$Pd), (ins sve_pred_enum:$pattern),
asm, "\t$Pd, $pattern",
"",
- []>, Sched<[]> {
+ [(set (vt pprty:$Pd), (op sve_pred_enum:$pattern))]>, Sched<[]> {
bits<4> Pd;
bits<5> pattern;
let Inst{31-24} = 0b00100101;
@@ -269,11 +270,11 @@ class sve_int_ptrue<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty>
let Defs = !if(!eq (opc{0}, 1), [NZCV], []);
}
-multiclass sve_int_ptrue<bits<3> opc, string asm> {
- def _B : sve_int_ptrue<0b00, opc, asm, PPR8>;
- def _H : sve_int_ptrue<0b01, opc, asm, PPR16>;
- def _S : sve_int_ptrue<0b10, opc, asm, PPR32>;
- def _D : sve_int_ptrue<0b11, opc, asm, PPR64>;
+multiclass sve_int_ptrue<bits<3> opc, string asm, SDPatternOperator op> {
+ def _B : sve_int_ptrue<0b00, opc, asm, PPR8, nxv16i1, op>;
+ def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
+ def _S : sve_int_ptrue<0b10, opc, asm, PPR32, nxv4i1, op>;
+ def _D : sve_int_ptrue<0b11, opc, asm, PPR64, nxv2i1, op>;
def : InstAlias<asm # "\t$Pd",
(!cast<Instruction>(NAME # _B) PPR8:$Pd, 0b11111), 1>;
@@ -285,9 +286,12 @@ multiclass sve_int_ptrue<bits<3> opc, string asm> {
(!cast<Instruction>(NAME # _D) PPR64:$Pd, 0b11111), 1>;
}
+def SDT_AArch64PTrue : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
+def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>;
+
let Predicates = [HasSVE] in {
- defm PTRUE : sve_int_ptrue<0b000, "ptrue">;
- defm PTRUES : sve_int_ptrue<0b001, "ptrues">;
+ defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
+ defm PTRUES : sve_int_ptrue<0b001, "ptrues", null_frag>;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
new file mode 100644
index 00000000000..b7131d31918
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
@@ -0,0 +1,42 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; PTRUE
+;
+
+define <vscale x 16 x i1> @ptrue_b8() {
+; CHECK-LABEL: ptrue_b8:
+; CHECK: ptrue p0.b, pow2
+; CHECK-NEXT: ret
+ %out = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
+ ret <vscale x 16 x i1> %out
+}
+
+define <vscale x 8 x i1> @ptrue_b16() {
+; CHECK-LABEL: ptrue_b16:
+; CHECK: ptrue p0.h, vl1
+; CHECK-NEXT: ret
+ %out = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 1)
+ ret <vscale x 8 x i1> %out
+}
+
+define <vscale x 4 x i1> @ptrue_b32() {
+; CHECK-LABEL: ptrue_b32:
+; CHECK: ptrue p0.s, mul3
+; CHECK-NEXT: ret
+ %out = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 30)
+ ret <vscale x 4 x i1> %out
+}
+
+define <vscale x 2 x i1> @ptrue_b64() {
+; CHECK-LABEL: ptrue_b64:
+; CHECK: ptrue p0.d
+; CHECK-NEXT: ret
+ %out = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
+ ret <vscale x 2 x i1> %out
+}
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
+declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 %pattern)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 %pattern)
+declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 %pattern)
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