diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/VOP3Instructions.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/mul.ll | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index aa041aab51c..666b80107dc 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -399,8 +399,10 @@ def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_ } // End Constraints = "@earlyclobber $vdst" let isCommutable = 1 in { +let SchedRW = [WriteDouble, WriteSALU] in { def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>; def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>; +} // End SchedRW = [WriteDouble, WriteSALU] } // End isCommutable = 1 } // End SubtargetPredicate = isCIVI diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll index 8839fcdffbc..555c65a6ffe 100644 --- a/llvm/test/CodeGen/AMDGPU/mul.ll +++ b/llvm/test/CodeGen/AMDGPU/mul.ll @@ -227,10 +227,10 @@ endif: ; VI: s_mul_i32 -; VI: s_mul_i32 -; VI: v_mul_hi_u32 ; VI: v_mul_hi_u32 ; VI: v_mad_u64_u32 +; VI: s_mul_i32 +; VI: v_mul_hi_u32 ; VI: v_mad_u64_u32 ; VI: v_mad_u64_u32 @@ -254,7 +254,7 @@ define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b) ; GCN-DAG: v_mul_hi_u32 ; GCN-DAG: v_mul_lo_i32 ; GCN-DAG: v_mul_lo_i32 -; GCN: v_add_i32_e32 +; GCN-DAG: v_add_i32_e32 ; SI-DAG: v_mul_hi_u32 ; SI-DAG: v_mul_lo_i32 @@ -265,7 +265,7 @@ define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b) ; SI-DAG: v_mul_lo_i32 ; SI-DAG: v_mul_lo_i32 -; VI: v_mad_u64_u32 +; VI-DAG: v_mad_u64_u32 ; VI: v_mad_u64_u32 ; VI: v_mad_u64_u32 |
