diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/rotate.ll | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/rotate.ll | 14 |
4 files changed, 37 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index fd33f879d4c..428624cd894 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -220,6 +220,10 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, // AArch64 lacks both left-rotate and popcount instructions. setOperationAction(ISD::ROTL, MVT::i32, Expand); setOperationAction(ISD::ROTL, MVT::i64, Expand); + for (MVT VT : MVT::vector_valuetypes()) { + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + } // AArch64 doesn't have {U|S}MUL_LOHI. setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 49f8918b8dd..91edc12dc11 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -718,7 +718,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, } // ARM does not have ROTL. - setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i32, Expand); + for (MVT VT : MVT::vector_valuetypes()) { + setOperationAction(ISD::ROTL, VT, Expand); + setOperationAction(ISD::ROTR, VT, Expand); + } setOperationAction(ISD::CTTZ, MVT::i32, Custom); setOperationAction(ISD::CTPOP, MVT::i32, Expand); if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) diff --git a/llvm/test/CodeGen/AArch64/rotate.ll b/llvm/test/CodeGen/AArch64/rotate.ll new file mode 100644 index 00000000000..5ac86d5f59c --- /dev/null +++ b/llvm/test/CodeGen/AArch64/rotate.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=aarch64--linux-gnueabihf | FileCheck %s + +;; This used to cause a backend crash about not being able to +;; select ROTL. Make sure if generates the basic ushr/shl. +define <2 x i64> @testcase(<2 x i64>* %in) { +; CHECK-LABEL: testcase +; CHECK: ushr {{v[0-9]+}}.2d +; CHECK: shl {{v[0-9]+}}.2d + %1 = load <2 x i64>, <2 x i64>* %in + %2 = lshr <2 x i64> %1, <i64 8, i64 8> + %3 = shl <2 x i64> %1, <i64 56, i64 56> + %4 = or <2 x i64> %2, %3 + ret <2 x i64> %4 +} diff --git a/llvm/test/CodeGen/ARM/rotate.ll b/llvm/test/CodeGen/ARM/rotate.ll new file mode 100644 index 00000000000..f3f7de2160f --- /dev/null +++ b/llvm/test/CodeGen/ARM/rotate.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=thumbv8--linux-gnueabihf | FileCheck %s + +;; This used to cause a backend crash about not being able to +;; select ROTL. Make sure if generates the basic VSHL/VSHR. +define <2 x i64> @testcase(<2 x i64>* %in) { +; CHECK-LABEL: testcase +; CHECK: vshl.i64 +; CHECK: vshr.u64 + %1 = load <2 x i64>, <2 x i64>* %in + %2 = lshr <2 x i64> %1, <i64 8, i64 8> + %3 = shl <2 x i64> %1, <i64 56, i64 56> + %4 = or <2 x i64> %2, %3 + ret <2 x i64> %4 +} |
