diff options
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsHexagon.td | 14841 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/Hexagon.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 3307 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 1537 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/multi-cycle.ll | 4 |
5 files changed, 8697 insertions, 10994 deletions
diff --git a/llvm/include/llvm/IR/IntrinsicsHexagon.td b/llvm/include/llvm/IR/IntrinsicsHexagon.td index 25f4215d68a..889662d9411 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagon.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagon.td @@ -15,7 +15,7 @@ // // All Hexagon intrinsics start with "llvm.hexagon.". let TargetPrefix = "hexagon" in { - /// Hexagon_Intrinsic - Base class for all Hexagon intrinsics. + /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, list<LLVMType> param_types, list<IntrinsicProperty> properties> @@ -30,397 +30,6 @@ let TargetPrefix = "hexagon" in { : Intrinsic<ret_types, param_types, properties>; } -//===----------------------------------------------------------------------===// -// -// DEF_FUNCTION_TYPE_1(QI_ftype_MEM,BT_BOOL,BT_PTR) -> -// Hexagon_qi_mem_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_mem_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_ptr_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(HI_ftype_SI,BT_I16,BT_INT) -> -// Hexagon_hi_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_hi_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i16_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(SI_ftype_SI,BT_INT,BT_INT) -> -// Hexagon_si_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(DI_ftype_SI,BT_LONGLONG,BT_INT) -> -// Hexagon_di_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(SI_ftype_DI,BT_INT,BT_LONGLONG) -> -// Hexagon_si_di_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_di_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(DI_ftype_DI,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_di_di_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_di_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(QI_ftype_QI,BT_BOOL,BT_BOOL) -> -// Hexagon_qi_qi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_qi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(QI_ftype_SI,BT_BOOL,BT_INT) -> -// Hexagon_qi_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(DI_ftype_QI,BT_LONGLONG,BT_BOOL) -> -// Hexagon_di_qi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_qi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_1(SI_ftype_QI,BT_INT,BT_BOOL) -> -// Hexagon_si_qi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_qi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_SISI,BT_BOOL,BT_INT,BT_INT) -> -// Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(void_ftype_SISI,BT_VOID,BT_INT,BT_INT) -> -// Hexagon_void_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_void_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_SISI,BT_INT,BT_INT,BT_INT) -> -// Hexagon_si_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(USI_ftype_SISI,BT_UINT,BT_INT,BT_INT) -> -// Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_usi_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(DI_ftype_SISI,BT_LONGLONG,BT_INT,BT_INT) -> -// Hexagon_di_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(UDI_ftype_SISI,BT_ULONGLONG,BT_INT,BT_INT) -> -// Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_udi_sisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(DI_ftype_SIDI,BT_LONGLONG,BT_INT,BT_LONGLONG) -> -// Hexagon_di_sidi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_sidi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(DI_ftype_DISI,BT_LONGLONG,BT_LONGLONG,BT_INT) -> -// Hexagon_di_disi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_disi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_SIDI,BT_INT,BT_INT,BT_LONGLONG) -> -// Hexagon_si_sidi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sidi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_DIDI,BT_INT,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_si_didi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_didi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i64_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(DI_ftype_DIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_di_didi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_didi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(UDI_ftype_DIDI,BT_ULONGLONG,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_udi_didi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_udi_didi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_DISI,BT_INT,BT_LONGLONG,BT_INT) -> -// Hexagon_si_disi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_disi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_DIDI,BT_BOOL,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_qi_didi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_didi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i64_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_SIDI,BT_BOOL,BT_INT,BT_LONGLONG) -> -// Hexagon_qi_didi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_sidi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i32_ty, llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_DISI,BT_BOOL,BT_LONGLONG,BT_INT) -> -// Hexagon_qi_disi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_disi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i64_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_QIQI,BT_BOOL,BT_BOOL,BT_BOOL) -> -// Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_qiqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(QI_ftype_QIQIQI,BT_BOOL,BT_BOOL,BT_BOOL) -> -// Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_qiqiqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_i1_ty, llvm_i1_ty, llvm_i1_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_QIQI,BT_INT,BT_BOOL,BT_BOOL) -> -// Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_qiqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_2(SI_ftype_QISI,BT_INT,BT_BOOL,BT_INT) -> -// Hexagon_si_qisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_qisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i1_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(void_ftype_SISISI,BT_VOID,BT_INT,BT_INT,BT_INT) -> -// Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_void_sisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_void_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_SISISI,BT_INT,BT_INT,BT_INT,BT_INT) -> -// Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_SISISI,BT_LONGLONG,BT_INT,BT_INT,BT_INT) -> -// Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_sisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_DISISI,BT_INT,BT_LONGLONG,BT_INT,BT_INT) -> -// Hexagon_si_disisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_disisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i64_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_DISISI,BT_LONGLONG,BT_LONGLONG,BT_INT,BT_INT) -> -// Hexagon_di_disisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_disisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_SIDISI,BT_INT,BT_INT,BT_LONGLONG,BT_INT) -> -// Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sidisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_DIDISI,BT_LONGLONG,BT_LONGLONG, -// BT_LONGLONG,BT_INT) -> -// Hexagon_di_didisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_didisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_SIDIDI,BT_INT,BT_INT,BT_LONGLONG,BT_LONGLONG) -> -// Hexagon_si_sididi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sididi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty, - llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_DIDIDI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG, -// BT_LONGLONG) -> -// Hexagon_di_dididi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_dididi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, - llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_SISIDI,BT_INT,BT_INT,BT_INT,BT_LONGLONG) -> -// Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sisidi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(SI_ftype_QISISI,BT_INT,BT_BOOL,BT_INT,BT_INT) -> -// Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_qisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_QISISI,BT_LONGLONG,BT_BOOL,BT_INT,BT_INT) -> -// Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_qisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i1_ty, llvm_i32_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_QIDIDI,BT_LONGLONG,BT_BOOL,BT_LONGLONG, -// BT_LONGLONG) -> -// Hexagon_di_qididi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_qididi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty, - llvm_i64_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_3(DI_ftype_DIDIQI,BT_LONGLONG,BT_LONGLONG,BT_LONGLONG, -// BT_BOOL) -> -// Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_didiqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, - llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_4(SI_ftype_SISISISI,BT_INT,BT_INT,BT_INT,BT_INT,BT_INT) -> -// Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sisisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// DEF_FUNCTION_TYPE_4(DI_ftype_DIDISISI,BT_LONGLONG,BT_LONGLONG, -// BT_LONGLONG,BT_INT,BT_INT) -> -// Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_didisisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, - llvm_i32_ty, llvm_i32_ty], - [IntrNoMem]>; - class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, @@ -457,191 +66,6 @@ class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix> llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>; -class Hexagon_v256_v256v256_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty], - [IntrArgMemOnly]>; - -// -// Hexagon_sf_df_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_i32_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_sf_df_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_df_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_double_ty], - [IntrNoMem]>; -// -// Hexagon_sf_di_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_di_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_i64_ty], - [IntrNoMem]>; -// -// Hexagon_df_sf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_sf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_float_ty], - [IntrNoMem]>; -// -// Hexagon_di_sf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_sf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_float_ty], - [IntrNoMem]>; -// -// Hexagon_sf_sf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_sf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_float_ty], - [IntrNoMem]>; -// -// Hexagon_si_sf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_float_ty], - [IntrNoMem]>; -// -// Hexagon_si_df_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_df_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_double_ty], - [IntrNoMem]>; -// -// Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_sfsf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_float_ty, llvm_float_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sfsf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_float_ty, llvm_float_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_sfsi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_float_ty, llvm_i32_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_qi_sfqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i1_ty], [llvm_float_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_sfsfsf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_float_ty, llvm_float_ty, - llvm_float_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_sf_sfsfsfqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_float_ty], [llvm_float_ty, llvm_float_ty, - llvm_float_ty, - llvm_i32_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_di_dididi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_dididisi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, - llvm_i64_ty, llvm_i32_ty], - [IntrNoMem]>; -// -// Hexagon_df_si_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_si_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_i32_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_df_di_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_di_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_i64_ty], - [IntrNoMem]>; -// -// Hexagon_di_df_Intrinsic<string GCCIntSuffix> -// -class Hexagon_di_df_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_double_ty], - [IntrNoMem]>; -// -// Hexagon_df_df_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_df_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_double_ty], - [IntrNoMem]>; -// -// Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_dfdf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_double_ty, llvm_double_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_dfdf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_double_ty, llvm_double_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix> -// -class Hexagon_si_dfsi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_double_ty, llvm_i32_ty], - [IntrNoMem, Throws]>; -// -// -// Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_double_ty, llvm_double_ty, - llvm_double_ty], - [IntrNoMem, Throws]>; -// -// Hexagon_df_dfdfdf_Intrinsic<string GCCIntSuffix> -// -class Hexagon_df_dfdfdfqi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_double_ty], [llvm_double_ty, llvm_double_ty, - llvm_double_ty, - llvm_i32_ty], - [IntrNoMem, Throws]>; - - -// This one below will not be auto-generated, -// so make sure, you don't overwrite this one. // // BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4) // @@ -699,4204 +123,6 @@ Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">; def int_hexagon_circ_stb : Hexagon_mem_memsisisi_Intrinsic<"circ_stb">; - -def int_hexagon_mm256i_vaddw : -Hexagon_v256_v256v256_Intrinsic<"_mm256i_vaddw">; - - -// This one above will not be auto-generated, -// so make sure, you don't overwrite this one. -// -// BUILTIN_INFO(HEXAGON.C2_cmpeq,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpeq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeq">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgt,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgt : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgt">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgtu,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgtu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtu">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpeqp,QI_ftype_DIDI,2) -// -def int_hexagon_C2_cmpeqp : -Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpeqp">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgtp,QI_ftype_DIDI,2) -// -def int_hexagon_C2_cmpgtp : -Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtp">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgtup,QI_ftype_DIDI,2) -// -def int_hexagon_C2_cmpgtup : -Hexagon_si_didi_Intrinsic<"HEXAGON_C2_cmpgtup">; -// -// BUILTIN_INFO(HEXAGON.A4_rcmpeqi,SI_ftype_SISI,2) -// -def int_hexagon_A4_rcmpeqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeqi">; -// -// BUILTIN_INFO(HEXAGON.A4_rcmpneqi,SI_ftype_SISI,2) -// -def int_hexagon_A4_rcmpneqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneqi">; -// -// BUILTIN_INFO(HEXAGON.A4_rcmpeq,SI_ftype_SISI,2) -// -def int_hexagon_A4_rcmpeq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpeq">; -// -// BUILTIN_INFO(HEXAGON.A4_rcmpneq,SI_ftype_SISI,2) -// -def int_hexagon_A4_rcmpneq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_rcmpneq">; -// -// BUILTIN_INFO(HEXAGON.C2_bitsset,QI_ftype_SISI,2) -// -def int_hexagon_C2_bitsset : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsset">; -// -// BUILTIN_INFO(HEXAGON.C2_bitsclr,QI_ftype_SISI,2) -// -def int_hexagon_C2_bitsclr : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclr">; -// -// BUILTIN_INFO(HEXAGON.C4_nbitsset,QI_ftype_SISI,2) -// -def int_hexagon_C4_nbitsset : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsset">; -// -// BUILTIN_INFO(HEXAGON.C4_nbitsclr,QI_ftype_SISI,2) -// -def int_hexagon_C4_nbitsclr : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclr">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpeqi,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpeqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpeqi">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgti,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgti : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgti">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgtui,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgtui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgtui">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgei,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgei : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgei">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpgeui,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpgeui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpgeui">; -// -// BUILTIN_INFO(HEXAGON.C2_cmplt,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmplt : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmplt">; -// -// BUILTIN_INFO(HEXAGON.C2_cmpltu,QI_ftype_SISI,2) -// -def int_hexagon_C2_cmpltu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_cmpltu">; -// -// BUILTIN_INFO(HEXAGON.C2_bitsclri,QI_ftype_SISI,2) -// -def int_hexagon_C2_bitsclri : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_bitsclri">; -// -// BUILTIN_INFO(HEXAGON.C4_nbitsclri,QI_ftype_SISI,2) -// -def int_hexagon_C4_nbitsclri : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_nbitsclri">; -// -// BUILTIN_INFO(HEXAGON.C4_cmpneqi,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmpneqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneqi">; -// -// BUILTIN_INFO(HEXAGON.C4_cmpltei,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmpltei : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpltei">; -// -// BUILTIN_INFO(HEXAGON.C4_cmplteui,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmplteui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteui">; -// -// BUILTIN_INFO(HEXAGON.C4_cmpneq,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmpneq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmpneq">; -// -// BUILTIN_INFO(HEXAGON.C4_cmplte,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmplte : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplte">; -// -// BUILTIN_INFO(HEXAGON.C4_cmplteu,QI_ftype_SISI,2) -// -def int_hexagon_C4_cmplteu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C4_cmplteu">; -// -// BUILTIN_INFO(HEXAGON.C2_and,QI_ftype_QIQI,2) -// -def int_hexagon_C2_and : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_and">; -// -// BUILTIN_INFO(HEXAGON.C2_or,QI_ftype_QIQI,2) -// -def int_hexagon_C2_or : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_or">; -// -// BUILTIN_INFO(HEXAGON.C2_xor,QI_ftype_QIQI,2) -// -def int_hexagon_C2_xor : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_xor">; -// -// BUILTIN_INFO(HEXAGON.C2_andn,QI_ftype_QIQI,2) -// -def int_hexagon_C2_andn : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_andn">; -// -// BUILTIN_INFO(HEXAGON.C2_not,QI_ftype_QI,1) -// -def int_hexagon_C2_not : -Hexagon_si_si_Intrinsic<"HEXAGON_C2_not">; -// -// BUILTIN_INFO(HEXAGON.C2_orn,QI_ftype_QIQI,2) -// -def int_hexagon_C2_orn : -Hexagon_si_sisi_Intrinsic<"HEXAGON_C2_orn">; -// -// BUILTIN_INFO(HEXAGON.C4_and_and,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_and_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_and">; -// -// BUILTIN_INFO(HEXAGON.C4_and_or,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_and_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_or">; -// -// BUILTIN_INFO(HEXAGON.C4_or_and,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_or_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_and">; -// -// BUILTIN_INFO(HEXAGON.C4_or_or,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_or_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_or">; -// -// BUILTIN_INFO(HEXAGON.C4_and_andn,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_and_andn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_andn">; -// -// BUILTIN_INFO(HEXAGON.C4_and_orn,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_and_orn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_and_orn">; -// -// BUILTIN_INFO(HEXAGON.C4_or_andn,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_or_andn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_andn">; -// -// BUILTIN_INFO(HEXAGON.C4_or_orn,QI_ftype_QIQIQI,3) -// -def int_hexagon_C4_or_orn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_C4_or_orn">; -// -// BUILTIN_INFO(HEXAGON.C2_pxfer_map,QI_ftype_QI,1) -// -def int_hexagon_C2_pxfer_map : -Hexagon_si_qi_Intrinsic<"HEXAGON_C2_pxfer_map">; -// -// BUILTIN_INFO(HEXAGON.C2_any8,QI_ftype_QI,1) -// -def int_hexagon_C2_any8 : -Hexagon_si_qi_Intrinsic<"HEXAGON_C2_any8">; -// -// BUILTIN_INFO(HEXAGON.C2_all8,QI_ftype_QI,1) -// -def int_hexagon_C2_all8 : -Hexagon_si_qi_Intrinsic<"HEXAGON_C2_all8">; -// -// BUILTIN_INFO(HEXAGON.C2_vitpack,SI_ftype_QIQI,2) -// -def int_hexagon_C2_vitpack : -Hexagon_si_qiqi_Intrinsic<"HEXAGON_C2_vitpack">; -// -// BUILTIN_INFO(HEXAGON.C2_mux,SI_ftype_QISISI,3) -// -def int_hexagon_C2_mux : -Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_mux">; -// -// BUILTIN_INFO(HEXAGON.C2_muxii,SI_ftype_QISISI,3) -// -def int_hexagon_C2_muxii : -Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxii">; -// -// BUILTIN_INFO(HEXAGON.C2_muxir,SI_ftype_QISISI,3) -// -def int_hexagon_C2_muxir : -Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxir">; -// -// BUILTIN_INFO(HEXAGON.C2_muxri,SI_ftype_QISISI,3) -// -def int_hexagon_C2_muxri : -Hexagon_si_qisisi_Intrinsic<"HEXAGON_C2_muxri">; -// -// BUILTIN_INFO(HEXAGON.C2_vmux,DI_ftype_QIDIDI,3) -// -def int_hexagon_C2_vmux : -Hexagon_di_qididi_Intrinsic<"HEXAGON_C2_vmux">; -// -// BUILTIN_INFO(HEXAGON.C2_mask,DI_ftype_QI,1) -// -def int_hexagon_C2_mask : -Hexagon_di_qi_Intrinsic<"HEXAGON_C2_mask">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpbeq,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpbeq : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbeq">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpbeqi,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpbeqi : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbeqi">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpbeq_any,QI_ftype_DIDI,2) -// -def int_hexagon_A4_vcmpbeq_any : -Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpbgtu,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpbgtu : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpbgtu">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpbgtui,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpbgtui : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgtui">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpbgt,QI_ftype_DIDI,2) -// -def int_hexagon_A4_vcmpbgt : -Hexagon_si_didi_Intrinsic<"HEXAGON_A4_vcmpbgt">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpbgti,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpbgti : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpbgti">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbeq,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbeq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeq">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbeqi,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbeqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbeqi">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbgtu,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbgtu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtu">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbgtui,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbgtui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgtui">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbgt,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbgt : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgt">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpbgti,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpbgti : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpbgti">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpheq,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpheq : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpheq">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmphgt,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmphgt : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgt">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmphgtu,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmphgtu : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmphgtu">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpheqi,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpheqi : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpheqi">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmphgti,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmphgti : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgti">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmphgtui,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmphgtui : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmphgtui">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpheq,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpheq : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheq">; -// -// BUILTIN_INFO(HEXAGON.A4_cmphgt,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmphgt : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgt">; -// -// BUILTIN_INFO(HEXAGON.A4_cmphgtu,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmphgtu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtu">; -// -// BUILTIN_INFO(HEXAGON.A4_cmpheqi,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmpheqi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmpheqi">; -// -// BUILTIN_INFO(HEXAGON.A4_cmphgti,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmphgti : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgti">; -// -// BUILTIN_INFO(HEXAGON.A4_cmphgtui,QI_ftype_SISI,2) -// -def int_hexagon_A4_cmphgtui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cmphgtui">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpweq,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpweq : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpweq">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpwgt,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpwgt : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgt">; -// -// BUILTIN_INFO(HEXAGON.A2_vcmpwgtu,QI_ftype_DIDI,2) -// -def int_hexagon_A2_vcmpwgtu : -Hexagon_si_didi_Intrinsic<"HEXAGON_A2_vcmpwgtu">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpweqi,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpweqi : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpweqi">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpwgti,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpwgti : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgti">; -// -// BUILTIN_INFO(HEXAGON.A4_vcmpwgtui,QI_ftype_DISI,2) -// -def int_hexagon_A4_vcmpwgtui : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_vcmpwgtui">; -// -// BUILTIN_INFO(HEXAGON.A4_boundscheck,QI_ftype_SIDI,2) -// -def int_hexagon_A4_boundscheck : -Hexagon_si_sidi_Intrinsic<"HEXAGON_A4_boundscheck">; -// -// BUILTIN_INFO(HEXAGON.A4_tlbmatch,QI_ftype_DISI,2) -// -def int_hexagon_A4_tlbmatch : -Hexagon_si_disi_Intrinsic<"HEXAGON_A4_tlbmatch">; -// -// BUILTIN_INFO(HEXAGON.C2_tfrpr,SI_ftype_QI,1) -// -def int_hexagon_C2_tfrpr : -Hexagon_si_qi_Intrinsic<"HEXAGON_C2_tfrpr">; -// -// BUILTIN_INFO(HEXAGON.C2_tfrrp,QI_ftype_SI,1) -// -def int_hexagon_C2_tfrrp : -Hexagon_si_si_Intrinsic<"HEXAGON_C2_tfrrp">; -// -// BUILTIN_INFO(HEXAGON.C4_fastcorner9,QI_ftype_QIQI,2) -// -def int_hexagon_C4_fastcorner9 : -Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9">; -// -// BUILTIN_INFO(HEXAGON.C4_fastcorner9_not,QI_ftype_QIQI,2) -// -def int_hexagon_C4_fastcorner9_not : -Hexagon_si_qiqi_Intrinsic<"HEXAGON_C4_fastcorner9_not">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_acc_sat_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_acc_sat_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_nac_sat_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpy_nac_sat_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_hh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_hh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_hh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_hh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_hl_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_hl_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_hl_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_hl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_lh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_lh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_lh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_lh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_ll_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_ll_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_ll_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_ll_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_hh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_hh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_hl_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_hl_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_hl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_lh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_lh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_lh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_ll_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_ll_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_ll_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_hh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_hh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_hl_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_hl_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_hl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_lh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_lh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_lh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_ll_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_rnd_ll_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_rnd_ll_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_hh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_hh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_hl_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_hl_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_hl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_lh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_lh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_lh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_ll_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_sat_rnd_ll_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_sat_rnd_ll_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_hh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_hh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_hl_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_hl_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_hl_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_lh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_lh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_lh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_ll_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_acc_ll_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_acc_ll_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_hh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_hh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_hl_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_hl_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_hl_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_lh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_lh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_lh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_ll_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_nac_ll_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyd_nac_ll_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_hh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_hh_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_hh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_hl_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_hl_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_hl_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_lh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_lh_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_lh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_ll_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_ll_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_ll_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_hh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hh_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_hh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_hl_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_hl_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_hl_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_lh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_lh_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_lh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_ll_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyd_rnd_ll_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_mpyd_rnd_ll_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_acc_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_acc_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_hh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_hh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_hl_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_hl_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_hl_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_lh_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_lh_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_lh_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s0,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_ll_s0 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_nac_ll_s1,SI_ftype_SISISI,3) -// -def int_hexagon_M2_mpyu_nac_ll_s1 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s0,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_hh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_hh_s1,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_hh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s0,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_hl_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_hl_s1,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_hl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s0,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_lh_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_lh_s1,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_lh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s0,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_ll_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_ll_s1,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_ll_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_hh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_hh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_hl_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_hl_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_hl_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_lh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_lh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_lh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_ll_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_acc_ll_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_acc_ll_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_hh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_hh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_hl_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_hl_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_hl_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_lh_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_lh_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_lh_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_ll_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_nac_ll_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_mpyud_nac_ll_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s0,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_hh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_hh_s1,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_hh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s0,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_hl_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_hl_s1,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_hl_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s0,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_lh_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_lh_s1,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_lh_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s0,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_ll_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyud_ll_s1,UDI_ftype_SISI,2) -// -def int_hexagon_M2_mpyud_ll_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpysmi,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpysmi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysmi">; -// -// BUILTIN_INFO(HEXAGON.M2_macsip,SI_ftype_SISISI,3) -// -def int_hexagon_M2_macsip : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsip">; -// -// BUILTIN_INFO(HEXAGON.M2_macsin,SI_ftype_SISISI,3) -// -def int_hexagon_M2_macsin : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_macsin">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyss_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_dpmpyss_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyss_acc_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_dpmpyss_acc_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyss_nac_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_dpmpyss_nac_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_s0,UDI_ftype_SISI,2) -// -def int_hexagon_M2_dpmpyuu_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_acc_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_dpmpyuu_acc_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyuu_nac_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_dpmpyuu_nac_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_up,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_up : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_up_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_up_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mpy_up_s1_sat,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpy_up_s1_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyu_up,USI_ftype_SISI,2) -// -def int_hexagon_M2_mpyu_up : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyu_up">; -// -// BUILTIN_INFO(HEXAGON.M2_mpysu_up,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpysu_up : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpysu_up">; -// -// BUILTIN_INFO(HEXAGON.M2_dpmpyss_rnd_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_dpmpyss_rnd_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_mac_up_s1_sat,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mac_up_s1_sat : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; -// -// BUILTIN_INFO(HEXAGON.M4_nac_up_s1_sat,SI_ftype_SISISI,3) -// -def int_hexagon_M4_nac_up_s1_sat : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyi,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpyi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyi">; -// -// BUILTIN_INFO(HEXAGON.M2_mpyui,SI_ftype_SISI,2) -// -def int_hexagon_M2_mpyui : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_mpyui">; -// -// BUILTIN_INFO(HEXAGON.M2_maci,SI_ftype_SISISI,3) -// -def int_hexagon_M2_maci : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_maci">; -// -// BUILTIN_INFO(HEXAGON.M2_acci,SI_ftype_SISISI,3) -// -def int_hexagon_M2_acci : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_acci">; -// -// BUILTIN_INFO(HEXAGON.M2_accii,SI_ftype_SISISI,3) -// -def int_hexagon_M2_accii : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_accii">; -// -// BUILTIN_INFO(HEXAGON.M2_nacci,SI_ftype_SISISI,3) -// -def int_hexagon_M2_nacci : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_nacci">; -// -// BUILTIN_INFO(HEXAGON.M2_naccii,SI_ftype_SISISI,3) -// -def int_hexagon_M2_naccii : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_naccii">; -// -// BUILTIN_INFO(HEXAGON.M2_subacc,SI_ftype_SISISI,3) -// -def int_hexagon_M2_subacc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_subacc">; -// -// BUILTIN_INFO(HEXAGON.M4_mpyrr_addr,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mpyrr_addr : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addr">; -// -// BUILTIN_INFO(HEXAGON.M4_mpyri_addr_u2,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mpyri_addr_u2 : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">; -// -// BUILTIN_INFO(HEXAGON.M4_mpyri_addr,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mpyri_addr : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addr">; -// -// BUILTIN_INFO(HEXAGON.M4_mpyri_addi,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mpyri_addi : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyri_addi">; -// -// BUILTIN_INFO(HEXAGON.M4_mpyrr_addi,SI_ftype_SISISI,3) -// -def int_hexagon_M4_mpyrr_addi : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_mpyrr_addi">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2s_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2s_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2s_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_vmac2s_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2s_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_vmac2s_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2s_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2su_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2su_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2su_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2su_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2su_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_vmac2su_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2su_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_vmac2su_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2su_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s0pack,SI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2s_s0pack : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2s_s1pack,SI_ftype_SISI,2) -// -def int_hexagon_M2_vmpy2s_s1pack : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2,DI_ftype_DISISI,3) -// -def int_hexagon_M2_vmac2 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_vmac2">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2es_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vmpy2es_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmpy2es_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vmpy2es_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2es_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vmac2es_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2es_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vmac2es_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vmac2es,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vmac2es : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vmac2es">; -// -// BUILTIN_INFO(HEXAGON.M2_vrmac_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vrmac_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrmac_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrmpy_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vrmpy_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrmpy_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s0,SI_ftype_DIDI,2) -// -def int_hexagon_M2_vdmpyrs_s0 : -Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmpyrs_s1,SI_ftype_DIDI,2) -// -def int_hexagon_M2_vdmpyrs_s1 : -Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; -// -// BUILTIN_INFO(HEXAGON.M5_vrmpybuu,DI_ftype_DIDI,2) -// -def int_hexagon_M5_vrmpybuu : -Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybuu">; -// -// BUILTIN_INFO(HEXAGON.M5_vrmacbuu,DI_ftype_DIDIDI,3) -// -def int_hexagon_M5_vrmacbuu : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbuu">; -// -// BUILTIN_INFO(HEXAGON.M5_vrmpybsu,DI_ftype_DIDI,2) -// -def int_hexagon_M5_vrmpybsu : -Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vrmpybsu">; -// -// BUILTIN_INFO(HEXAGON.M5_vrmacbsu,DI_ftype_DIDIDI,3) -// -def int_hexagon_M5_vrmacbsu : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vrmacbsu">; -// -// BUILTIN_INFO(HEXAGON.M5_vmpybuu,DI_ftype_SISI,2) -// -def int_hexagon_M5_vmpybuu : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybuu">; -// -// BUILTIN_INFO(HEXAGON.M5_vmpybsu,DI_ftype_SISI,2) -// -def int_hexagon_M5_vmpybsu : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M5_vmpybsu">; -// -// BUILTIN_INFO(HEXAGON.M5_vmacbuu,DI_ftype_DISISI,3) -// -def int_hexagon_M5_vmacbuu : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbuu">; -// -// BUILTIN_INFO(HEXAGON.M5_vmacbsu,DI_ftype_DISISI,3) -// -def int_hexagon_M5_vmacbsu : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M5_vmacbsu">; -// -// BUILTIN_INFO(HEXAGON.M5_vdmpybsu,DI_ftype_DIDI,2) -// -def int_hexagon_M5_vdmpybsu : -Hexagon_di_didi_Intrinsic<"HEXAGON_M5_vdmpybsu">; -// -// BUILTIN_INFO(HEXAGON.M5_vdmacbsu,DI_ftype_DIDIDI,3) -// -def int_hexagon_M5_vdmacbsu : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M5_vdmacbsu">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmacs_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vdmacs_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmacs_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vdmacs_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vdmacs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmpys_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vdmpys_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vdmpys_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vdmpys_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vdmpys_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyrs_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyrs_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyrs_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyrs_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s0,SI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyrsc_s0 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyrsc_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyrsc_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmacs_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmacs_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmacs_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmacs_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmacsc_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmacsc_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmacsc_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmacsc_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacsc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpys_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpys_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpys_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpys_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpys_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpysc_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpysc_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpysc_s1,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpysc_s1 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpysc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cnacs_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cnacs_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cnacs_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cnacs_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_cnacsc_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cnacsc_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cnacsc_s1,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cnacsc_s1 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cnacsc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1,DI_ftype_DISI,2) -// -def int_hexagon_M2_vrcmpys_s1 : -Hexagon_di_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpys_acc_s1,DI_ftype_DIDISI,3) -// -def int_hexagon_M2_vrcmpys_acc_s1 : -Hexagon_di_didisi_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpys_s1rp,SI_ftype_DISI,2) -// -def int_hexagon_M2_vrcmpys_s1rp : -Hexagon_si_disi_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacls_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacls_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacls_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacls_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmachs_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmachs_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmachs_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmachs_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyl_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyl_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyl_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyl_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyh_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyh_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyh_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyh_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacls_rs0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacls_rs0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacls_rs1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacls_rs1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacls_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmachs_rs0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmachs_rs0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmachs_rs1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmachs_rs1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmachs_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyl_rs0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyl_rs0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyl_rs1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyl_rs1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyh_rs0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyh_rs0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyh_rs1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyh_rs1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M4_vrmpyeh_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M4_vrmpyeh_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M4_vrmpyeh_acc_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyeh_acc_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M4_vrmpyeh_acc_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M4_vrmpyoh_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M4_vrmpyoh_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M4_vrmpyoh_acc_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_vrmpyoh_acc_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M4_vrmpyoh_acc_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_hmmpyl_rs1,SI_ftype_SISI,2) -// -def int_hexagon_M2_hmmpyl_rs1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_hmmpyh_rs1,SI_ftype_SISI,2) -// -def int_hexagon_M2_hmmpyh_rs1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_hmmpyl_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_hmmpyl_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_hmmpyh_s1,SI_ftype_SISI,2) -// -def int_hexagon_M2_hmmpyh_s1 : -Hexagon_si_sisi_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmaculs_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmaculs_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmaculs_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmaculs_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacuhs_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacuhs_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacuhs_s1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacuhs_s1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyul_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyul_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyul_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyul_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyuh_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyuh_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyuh_s1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyuh_s1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmaculs_rs0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmaculs_rs0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmaculs_rs1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmaculs_rs1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacuhs_rs0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmacuhs_rs1,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_mmacuhs_rs1 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyul_rs0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyul_rs0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyul_rs1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyul_rs1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyuh_rs0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; -// -// BUILTIN_INFO(HEXAGON.M2_mmpyuh_rs1,DI_ftype_DIDI,2) -// -def int_hexagon_M2_mmpyuh_rs1 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vrcmaci_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vrcmacr_s0 : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmaci_s0c,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vrcmaci_s0c : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmacr_s0c,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vrcmacr_s0c : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; -// -// BUILTIN_INFO(HEXAGON.M2_cmaci_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmaci_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmaci_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmacr_s0,DI_ftype_DISISI,3) -// -def int_hexagon_M2_cmacr_s0 : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M2_cmacr_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vrcmpyi_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vrcmpyr_s0 : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpyi_s0c,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vrcmpyi_s0c : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; -// -// BUILTIN_INFO(HEXAGON.M2_vrcmpyr_s0c,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vrcmpyr_s0c : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyi_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyi_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyi_s0">; -// -// BUILTIN_INFO(HEXAGON.M2_cmpyr_s0,DI_ftype_SISI,2) -// -def int_hexagon_M2_cmpyr_s0 : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M2_cmpyr_s0">; -// -// BUILTIN_INFO(HEXAGON.M4_cmpyi_wh,SI_ftype_DISI,2) -// -def int_hexagon_M4_cmpyi_wh : -Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_wh">; -// -// BUILTIN_INFO(HEXAGON.M4_cmpyr_wh,SI_ftype_DISI,2) -// -def int_hexagon_M4_cmpyr_wh : -Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_wh">; -// -// BUILTIN_INFO(HEXAGON.M4_cmpyi_whc,SI_ftype_DISI,2) -// -def int_hexagon_M4_cmpyi_whc : -Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyi_whc">; -// -// BUILTIN_INFO(HEXAGON.M4_cmpyr_whc,SI_ftype_DISI,2) -// -def int_hexagon_M4_cmpyr_whc : -Hexagon_si_disi_Intrinsic<"HEXAGON_M4_cmpyr_whc">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_i,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vcmpy_s0_sat_i : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmpy_s0_sat_r,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vcmpy_s0_sat_r : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_i,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vcmpy_s1_sat_i : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmpy_s1_sat_r,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vcmpy_s1_sat_r : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_i,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vcmac_s0_sat_i : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; -// -// BUILTIN_INFO(HEXAGON.M2_vcmac_s0_sat_r,DI_ftype_DIDIDI,3) -// -def int_hexagon_M2_vcmac_s0_sat_r : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; -// -// BUILTIN_INFO(HEXAGON.S2_vcrotate,DI_ftype_DISI,2) -// -def int_hexagon_S2_vcrotate : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcrotate">; -// -// BUILTIN_INFO(HEXAGON.S4_vrcrotate_acc,DI_ftype_DIDISISI,4) -// -def int_hexagon_S4_vrcrotate_acc : -Hexagon_di_didisisi_Intrinsic<"HEXAGON_S4_vrcrotate_acc">; -// -// BUILTIN_INFO(HEXAGON.S4_vrcrotate,DI_ftype_DISISI,3) -// -def int_hexagon_S4_vrcrotate : -Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_vrcrotate">; -// -// BUILTIN_INFO(HEXAGON.S2_vcnegh,DI_ftype_DISI,2) -// -def int_hexagon_S2_vcnegh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_vcnegh">; -// -// BUILTIN_INFO(HEXAGON.S2_vrcnegh,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_vrcnegh : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vrcnegh">; -// -// BUILTIN_INFO(HEXAGON.M4_pmpyw,DI_ftype_SISI,2) -// -def int_hexagon_M4_pmpyw : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_pmpyw">; -// -// BUILTIN_INFO(HEXAGON.M4_vpmpyh,DI_ftype_SISI,2) -// -def int_hexagon_M4_vpmpyh : -Hexagon_di_sisi_Intrinsic<"HEXAGON_M4_vpmpyh">; -// -// BUILTIN_INFO(HEXAGON.M4_pmpyw_acc,DI_ftype_DISISI,3) -// -def int_hexagon_M4_pmpyw_acc : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_pmpyw_acc">; -// -// BUILTIN_INFO(HEXAGON.M4_vpmpyh_acc,DI_ftype_DISISI,3) -// -def int_hexagon_M4_vpmpyh_acc : -Hexagon_di_disisi_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; -// -// BUILTIN_INFO(HEXAGON.A2_add,SI_ftype_SISI,2) -// -def int_hexagon_A2_add : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_add">; -// -// BUILTIN_INFO(HEXAGON.A2_sub,SI_ftype_SISI,2) -// -def int_hexagon_A2_sub : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_sub">; -// -// BUILTIN_INFO(HEXAGON.A2_addsat,SI_ftype_SISI,2) -// -def int_hexagon_A2_addsat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addsat">; -// -// BUILTIN_INFO(HEXAGON.A2_subsat,SI_ftype_SISI,2) -// -def int_hexagon_A2_subsat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subsat">; -// -// BUILTIN_INFO(HEXAGON.A2_addi,SI_ftype_SISI,2) -// -def int_hexagon_A2_addi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addi">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_l16_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_l16_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_l16_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_l16_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_l16_sat_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_l16_sat_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_l16_sat_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_l16_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_l16_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_l16_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_l16_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_l16_sat_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_l16_sat_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_l16_sat_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_lh,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_lh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_lh">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_hh,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_hh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_hh">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_sat_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_lh,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_sat_lh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_sat_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_addh_h16_sat_hh,SI_ftype_SISI,2) -// -def int_hexagon_A2_addh_h16_sat_hh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_lh,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_lh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_lh">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_hh,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_hh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_hh">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_sat_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_lh,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_sat_lh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_sat_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_subh_h16_sat_hh,SI_ftype_SISI,2) -// -def int_hexagon_A2_subh_h16_sat_hh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; -// -// BUILTIN_INFO(HEXAGON.A2_aslh,SI_ftype_SI,1) -// -def int_hexagon_A2_aslh : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_aslh">; -// -// BUILTIN_INFO(HEXAGON.A2_asrh,SI_ftype_SI,1) -// -def int_hexagon_A2_asrh : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_asrh">; -// -// BUILTIN_INFO(HEXAGON.A2_addp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_addp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addp">; -// -// BUILTIN_INFO(HEXAGON.A2_addpsat,DI_ftype_DIDI,2) -// -def int_hexagon_A2_addpsat : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_addpsat">; -// -// BUILTIN_INFO(HEXAGON.A2_addsp,DI_ftype_SIDI,2) -// -def int_hexagon_A2_addsp : -Hexagon_di_sidi_Intrinsic<"HEXAGON_A2_addsp">; -// -// BUILTIN_INFO(HEXAGON.A2_subp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_subp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_subp">; -// -// BUILTIN_INFO(HEXAGON.A2_neg,SI_ftype_SI,1) -// -def int_hexagon_A2_neg : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_neg">; -// -// BUILTIN_INFO(HEXAGON.A2_negsat,SI_ftype_SI,1) -// -def int_hexagon_A2_negsat : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_negsat">; -// -// BUILTIN_INFO(HEXAGON.A2_abs,SI_ftype_SI,1) -// -def int_hexagon_A2_abs : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_abs">; -// -// BUILTIN_INFO(HEXAGON.A2_abssat,SI_ftype_SI,1) -// -def int_hexagon_A2_abssat : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_abssat">; -// -// BUILTIN_INFO(HEXAGON.A2_vconj,DI_ftype_DI,1) -// -def int_hexagon_A2_vconj : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_vconj">; -// -// BUILTIN_INFO(HEXAGON.A2_negp,DI_ftype_DI,1) -// -def int_hexagon_A2_negp : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_negp">; -// -// BUILTIN_INFO(HEXAGON.A2_absp,DI_ftype_DI,1) -// -def int_hexagon_A2_absp : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_absp">; -// -// BUILTIN_INFO(HEXAGON.A2_max,SI_ftype_SISI,2) -// -def int_hexagon_A2_max : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_max">; -// -// BUILTIN_INFO(HEXAGON.A2_maxu,USI_ftype_SISI,2) -// -def int_hexagon_A2_maxu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_maxu">; -// -// BUILTIN_INFO(HEXAGON.A2_min,SI_ftype_SISI,2) -// -def int_hexagon_A2_min : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_min">; -// -// BUILTIN_INFO(HEXAGON.A2_minu,USI_ftype_SISI,2) -// -def int_hexagon_A2_minu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_minu">; -// -// BUILTIN_INFO(HEXAGON.A2_maxp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_maxp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxp">; -// -// BUILTIN_INFO(HEXAGON.A2_maxup,UDI_ftype_DIDI,2) -// -def int_hexagon_A2_maxup : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_maxup">; -// -// BUILTIN_INFO(HEXAGON.A2_minp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_minp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minp">; -// -// BUILTIN_INFO(HEXAGON.A2_minup,UDI_ftype_DIDI,2) -// -def int_hexagon_A2_minup : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_minup">; -// -// BUILTIN_INFO(HEXAGON.A2_tfr,SI_ftype_SI,1) -// -def int_hexagon_A2_tfr : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfr">; -// -// BUILTIN_INFO(HEXAGON.A2_tfrsi,SI_ftype_SI,1) -// -def int_hexagon_A2_tfrsi : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_tfrsi">; -// -// BUILTIN_INFO(HEXAGON.A2_tfrp,DI_ftype_DI,1) -// -def int_hexagon_A2_tfrp : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_tfrp">; -// -// BUILTIN_INFO(HEXAGON.A2_tfrpi,DI_ftype_SI,1) -// -def int_hexagon_A2_tfrpi : -Hexagon_di_si_Intrinsic<"HEXAGON_A2_tfrpi">; -// -// BUILTIN_INFO(HEXAGON.A2_zxtb,SI_ftype_SI,1) -// -def int_hexagon_A2_zxtb : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxtb">; -// -// BUILTIN_INFO(HEXAGON.A2_sxtb,SI_ftype_SI,1) -// -def int_hexagon_A2_sxtb : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxtb">; -// -// BUILTIN_INFO(HEXAGON.A2_zxth,SI_ftype_SI,1) -// -def int_hexagon_A2_zxth : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_zxth">; -// -// BUILTIN_INFO(HEXAGON.A2_sxth,SI_ftype_SI,1) -// -def int_hexagon_A2_sxth : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_sxth">; -// -// BUILTIN_INFO(HEXAGON.A2_combinew,DI_ftype_SISI,2) -// -def int_hexagon_A2_combinew : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combinew">; -// -// BUILTIN_INFO(HEXAGON.A4_combineri,DI_ftype_SISI,2) -// -def int_hexagon_A4_combineri : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineri">; -// -// BUILTIN_INFO(HEXAGON.A4_combineir,DI_ftype_SISI,2) -// -def int_hexagon_A4_combineir : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_combineir">; -// -// BUILTIN_INFO(HEXAGON.A2_combineii,DI_ftype_SISI,2) -// -def int_hexagon_A2_combineii : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A2_combineii">; -// -// BUILTIN_INFO(HEXAGON.A2_combine_hh,SI_ftype_SISI,2) -// -def int_hexagon_A2_combine_hh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hh">; -// -// BUILTIN_INFO(HEXAGON.A2_combine_hl,SI_ftype_SISI,2) -// -def int_hexagon_A2_combine_hl : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_hl">; -// -// BUILTIN_INFO(HEXAGON.A2_combine_lh,SI_ftype_SISI,2) -// -def int_hexagon_A2_combine_lh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_lh">; -// -// BUILTIN_INFO(HEXAGON.A2_combine_ll,SI_ftype_SISI,2) -// -def int_hexagon_A2_combine_ll : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_combine_ll">; -// -// BUILTIN_INFO(HEXAGON.A2_tfril,SI_ftype_SISI,2) -// -def int_hexagon_A2_tfril : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfril">; -// -// BUILTIN_INFO(HEXAGON.A2_tfrih,SI_ftype_SISI,2) -// -def int_hexagon_A2_tfrih : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_tfrih">; -// -// BUILTIN_INFO(HEXAGON.A2_and,SI_ftype_SISI,2) -// -def int_hexagon_A2_and : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_and">; -// -// BUILTIN_INFO(HEXAGON.A2_or,SI_ftype_SISI,2) -// -def int_hexagon_A2_or : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_or">; -// -// BUILTIN_INFO(HEXAGON.A2_xor,SI_ftype_SISI,2) -// -def int_hexagon_A2_xor : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_xor">; -// -// BUILTIN_INFO(HEXAGON.A2_not,SI_ftype_SI,1) -// -def int_hexagon_A2_not : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_not">; -// -// BUILTIN_INFO(HEXAGON.M2_xor_xacc,SI_ftype_SISISI,3) -// -def int_hexagon_M2_xor_xacc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M2_xor_xacc">; -// -// BUILTIN_INFO(HEXAGON.M4_xor_xacc,DI_ftype_DIDIDI,3) -// -def int_hexagon_M4_xor_xacc : -Hexagon_di_dididi_Intrinsic<"HEXAGON_M4_xor_xacc">; -// -// BUILTIN_INFO(HEXAGON.A4_andn,SI_ftype_SISI,2) -// -def int_hexagon_A4_andn : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_andn">; -// -// BUILTIN_INFO(HEXAGON.A4_orn,SI_ftype_SISI,2) -// -def int_hexagon_A4_orn : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_orn">; -// -// BUILTIN_INFO(HEXAGON.A4_andnp,DI_ftype_DIDI,2) -// -def int_hexagon_A4_andnp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A4_andnp">; -// -// BUILTIN_INFO(HEXAGON.A4_ornp,DI_ftype_DIDI,2) -// -def int_hexagon_A4_ornp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A4_ornp">; -// -// BUILTIN_INFO(HEXAGON.S4_addaddi,SI_ftype_SISISI,3) -// -def int_hexagon_S4_addaddi : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addaddi">; -// -// BUILTIN_INFO(HEXAGON.S4_subaddi,SI_ftype_SISISI,3) -// -def int_hexagon_S4_subaddi : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subaddi">; -// -// BUILTIN_INFO(HEXAGON.M4_and_and,SI_ftype_SISISI,3) -// -def int_hexagon_M4_and_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_and">; -// -// BUILTIN_INFO(HEXAGON.M4_and_andn,SI_ftype_SISISI,3) -// -def int_hexagon_M4_and_andn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_andn">; -// -// BUILTIN_INFO(HEXAGON.M4_and_or,SI_ftype_SISISI,3) -// -def int_hexagon_M4_and_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_or">; -// -// BUILTIN_INFO(HEXAGON.M4_and_xor,SI_ftype_SISISI,3) -// -def int_hexagon_M4_and_xor : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_and_xor">; -// -// BUILTIN_INFO(HEXAGON.M4_or_and,SI_ftype_SISISI,3) -// -def int_hexagon_M4_or_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_and">; -// -// BUILTIN_INFO(HEXAGON.M4_or_andn,SI_ftype_SISISI,3) -// -def int_hexagon_M4_or_andn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_andn">; -// -// BUILTIN_INFO(HEXAGON.M4_or_or,SI_ftype_SISISI,3) -// -def int_hexagon_M4_or_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_or">; -// -// BUILTIN_INFO(HEXAGON.M4_or_xor,SI_ftype_SISISI,3) -// -def int_hexagon_M4_or_xor : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_or_xor">; -// -// BUILTIN_INFO(HEXAGON.S4_or_andix,SI_ftype_SISISI,3) -// -def int_hexagon_S4_or_andix : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andix">; -// -// BUILTIN_INFO(HEXAGON.S4_or_andi,SI_ftype_SISISI,3) -// -def int_hexagon_S4_or_andi : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_andi">; -// -// BUILTIN_INFO(HEXAGON.S4_or_ori,SI_ftype_SISISI,3) -// -def int_hexagon_S4_or_ori : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_or_ori">; -// -// BUILTIN_INFO(HEXAGON.M4_xor_and,SI_ftype_SISISI,3) -// -def int_hexagon_M4_xor_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_and">; -// -// BUILTIN_INFO(HEXAGON.M4_xor_or,SI_ftype_SISISI,3) -// -def int_hexagon_M4_xor_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_or">; -// -// BUILTIN_INFO(HEXAGON.M4_xor_andn,SI_ftype_SISISI,3) -// -def int_hexagon_M4_xor_andn : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_M4_xor_andn">; -// -// BUILTIN_INFO(HEXAGON.A2_subri,SI_ftype_SISI,2) -// -def int_hexagon_A2_subri : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_subri">; -// -// BUILTIN_INFO(HEXAGON.A2_andir,SI_ftype_SISI,2) -// -def int_hexagon_A2_andir : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_andir">; -// -// BUILTIN_INFO(HEXAGON.A2_orir,SI_ftype_SISI,2) -// -def int_hexagon_A2_orir : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_orir">; -// -// BUILTIN_INFO(HEXAGON.A2_andp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_andp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_andp">; -// -// BUILTIN_INFO(HEXAGON.A2_orp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_orp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_orp">; -// -// BUILTIN_INFO(HEXAGON.A2_xorp,DI_ftype_DIDI,2) -// -def int_hexagon_A2_xorp : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_xorp">; -// -// BUILTIN_INFO(HEXAGON.A2_notp,DI_ftype_DI,1) -// -def int_hexagon_A2_notp : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_notp">; -// -// BUILTIN_INFO(HEXAGON.A2_sxtw,DI_ftype_SI,1) -// -def int_hexagon_A2_sxtw : -Hexagon_di_si_Intrinsic<"HEXAGON_A2_sxtw">; -// -// BUILTIN_INFO(HEXAGON.A2_sat,SI_ftype_DI,1) -// -def int_hexagon_A2_sat : -Hexagon_si_di_Intrinsic<"HEXAGON_A2_sat">; -// -// BUILTIN_INFO(HEXAGON.A2_roundsat,SI_ftype_DI,1) -// -def int_hexagon_A2_roundsat : -Hexagon_si_di_Intrinsic<"HEXAGON_A2_roundsat">; -// -// BUILTIN_INFO(HEXAGON.A2_sath,SI_ftype_SI,1) -// -def int_hexagon_A2_sath : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_sath">; -// -// BUILTIN_INFO(HEXAGON.A2_satuh,SI_ftype_SI,1) -// -def int_hexagon_A2_satuh : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_satuh">; -// -// BUILTIN_INFO(HEXAGON.A2_satub,SI_ftype_SI,1) -// -def int_hexagon_A2_satub : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_satub">; -// -// BUILTIN_INFO(HEXAGON.A2_satb,SI_ftype_SI,1) -// -def int_hexagon_A2_satb : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_satb">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddub">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddb_map,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddb_map : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddb_map">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddubs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddubs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddubs">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddh">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddhs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddhs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddhs">; -// -// BUILTIN_INFO(HEXAGON.A2_vadduhs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vadduhs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vadduhs">; -// -// BUILTIN_INFO(HEXAGON.A5_vaddhubs,SI_ftype_DIDI,2) -// -def int_hexagon_A5_vaddhubs : -Hexagon_si_didi_Intrinsic<"HEXAGON_A5_vaddhubs">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddw">; -// -// BUILTIN_INFO(HEXAGON.A2_vaddws,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vaddws : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vaddws">; -// -// BUILTIN_INFO(HEXAGON.S4_vxaddsubw,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxaddsubw : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubw">; -// -// BUILTIN_INFO(HEXAGON.S4_vxsubaddw,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxsubaddw : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddw">; -// -// BUILTIN_INFO(HEXAGON.S4_vxaddsubh,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxaddsubh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubh">; -// -// BUILTIN_INFO(HEXAGON.S4_vxsubaddh,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxsubaddh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddh">; -// -// BUILTIN_INFO(HEXAGON.S4_vxaddsubhr,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxaddsubhr : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxaddsubhr">; -// -// BUILTIN_INFO(HEXAGON.S4_vxsubaddhr,DI_ftype_DIDI,2) -// -def int_hexagon_S4_vxsubaddhr : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_vxsubaddhr">; -// -// BUILTIN_INFO(HEXAGON.A2_svavgh,SI_ftype_SISI,2) -// -def int_hexagon_A2_svavgh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavgh">; -// -// BUILTIN_INFO(HEXAGON.A2_svavghs,SI_ftype_SISI,2) -// -def int_hexagon_A2_svavghs : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svavghs">; -// -// BUILTIN_INFO(HEXAGON.A2_svnavgh,SI_ftype_SISI,2) -// -def int_hexagon_A2_svnavgh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svnavgh">; -// -// BUILTIN_INFO(HEXAGON.A2_svaddh,SI_ftype_SISI,2) -// -def int_hexagon_A2_svaddh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddh">; -// -// BUILTIN_INFO(HEXAGON.A2_svaddhs,SI_ftype_SISI,2) -// -def int_hexagon_A2_svaddhs : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svaddhs">; -// -// BUILTIN_INFO(HEXAGON.A2_svadduhs,SI_ftype_SISI,2) -// -def int_hexagon_A2_svadduhs : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svadduhs">; -// -// BUILTIN_INFO(HEXAGON.A2_svsubh,SI_ftype_SISI,2) -// -def int_hexagon_A2_svsubh : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubh">; -// -// BUILTIN_INFO(HEXAGON.A2_svsubhs,SI_ftype_SISI,2) -// -def int_hexagon_A2_svsubhs : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubhs">; -// -// BUILTIN_INFO(HEXAGON.A2_svsubuhs,SI_ftype_SISI,2) -// -def int_hexagon_A2_svsubuhs : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A2_svsubuhs">; -// -// BUILTIN_INFO(HEXAGON.A2_vraddub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vraddub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vraddub">; -// -// BUILTIN_INFO(HEXAGON.A2_vraddub_acc,DI_ftype_DIDIDI,3) -// -def int_hexagon_A2_vraddub_acc : -Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vraddub_acc">; -// -// BUILTIN_INFO(HEXAGON.M2_vraddh,SI_ftype_DIDI,2) -// -def int_hexagon_M2_vraddh : -Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vraddh">; -// -// BUILTIN_INFO(HEXAGON.M2_vradduh,SI_ftype_DIDI,2) -// -def int_hexagon_M2_vradduh : -Hexagon_si_didi_Intrinsic<"HEXAGON_M2_vradduh">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubub">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubb_map,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubb_map : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubb_map">; -// -// BUILTIN_INFO(HEXAGON.A2_vsububs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsububs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsububs">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubh">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubhs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubhs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubhs">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubuhs,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubuhs : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubuhs">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubw">; -// -// BUILTIN_INFO(HEXAGON.A2_vsubws,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vsubws : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vsubws">; -// -// BUILTIN_INFO(HEXAGON.A2_vabsh,DI_ftype_DI,1) -// -def int_hexagon_A2_vabsh : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsh">; -// -// BUILTIN_INFO(HEXAGON.A2_vabshsat,DI_ftype_DI,1) -// -def int_hexagon_A2_vabshsat : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabshsat">; -// -// BUILTIN_INFO(HEXAGON.A2_vabsw,DI_ftype_DI,1) -// -def int_hexagon_A2_vabsw : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabsw">; -// -// BUILTIN_INFO(HEXAGON.A2_vabswsat,DI_ftype_DI,1) -// -def int_hexagon_A2_vabswsat : -Hexagon_di_di_Intrinsic<"HEXAGON_A2_vabswsat">; -// -// BUILTIN_INFO(HEXAGON.M2_vabsdiffw,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vabsdiffw : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffw">; -// -// BUILTIN_INFO(HEXAGON.M2_vabsdiffh,DI_ftype_DIDI,2) -// -def int_hexagon_M2_vabsdiffh : -Hexagon_di_didi_Intrinsic<"HEXAGON_M2_vabsdiffh">; -// -// BUILTIN_INFO(HEXAGON.A2_vrsadub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vrsadub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vrsadub">; -// -// BUILTIN_INFO(HEXAGON.A2_vrsadub_acc,DI_ftype_DIDIDI,3) -// -def int_hexagon_A2_vrsadub_acc : -Hexagon_di_dididi_Intrinsic<"HEXAGON_A2_vrsadub_acc">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgub">; -// -// BUILTIN_INFO(HEXAGON.A2_vavguh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavguh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguh">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgh">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavgh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavgh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgh">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgw">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavgw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavgw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgw">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgwr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgwr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwr">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavgwr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavgwr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgwcr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgwcr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgwcr">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavgwcr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavgwcr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavgwcr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavghcr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavghcr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghcr">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavghcr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavghcr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghcr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavguw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavguw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguw">; -// -// BUILTIN_INFO(HEXAGON.A2_vavguwr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavguwr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguwr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavgubr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavgubr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavgubr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavguhr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavguhr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavguhr">; -// -// BUILTIN_INFO(HEXAGON.A2_vavghr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vavghr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vavghr">; -// -// BUILTIN_INFO(HEXAGON.A2_vnavghr,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vnavghr : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vnavghr">; -// -// BUILTIN_INFO(HEXAGON.A4_round_ri,SI_ftype_SISI,2) -// -def int_hexagon_A4_round_ri : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri">; -// -// BUILTIN_INFO(HEXAGON.A4_round_rr,SI_ftype_SISI,2) -// -def int_hexagon_A4_round_rr : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr">; -// -// BUILTIN_INFO(HEXAGON.A4_round_ri_sat,SI_ftype_SISI,2) -// -def int_hexagon_A4_round_ri_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_ri_sat">; -// -// BUILTIN_INFO(HEXAGON.A4_round_rr_sat,SI_ftype_SISI,2) -// -def int_hexagon_A4_round_rr_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_round_rr_sat">; -// -// BUILTIN_INFO(HEXAGON.A4_cround_ri,SI_ftype_SISI,2) -// -def int_hexagon_A4_cround_ri : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_ri">; -// -// BUILTIN_INFO(HEXAGON.A4_cround_rr,SI_ftype_SISI,2) -// -def int_hexagon_A4_cround_rr : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_cround_rr">; -// -// BUILTIN_INFO(HEXAGON.A4_vrminh,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrminh : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminh">; -// -// BUILTIN_INFO(HEXAGON.A4_vrmaxh,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrmaxh : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxh">; -// -// BUILTIN_INFO(HEXAGON.A4_vrminuh,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrminuh : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuh">; -// -// BUILTIN_INFO(HEXAGON.A4_vrmaxuh,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrmaxuh : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuh">; -// -// BUILTIN_INFO(HEXAGON.A4_vrminw,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrminw : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminw">; -// -// BUILTIN_INFO(HEXAGON.A4_vrmaxw,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrmaxw : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxw">; -// -// BUILTIN_INFO(HEXAGON.A4_vrminuw,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrminuw : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrminuw">; -// -// BUILTIN_INFO(HEXAGON.A4_vrmaxuw,DI_ftype_DIDISI,3) -// -def int_hexagon_A4_vrmaxuw : -Hexagon_di_didisi_Intrinsic<"HEXAGON_A4_vrmaxuw">; -// -// BUILTIN_INFO(HEXAGON.A2_vminb,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminb : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminb">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxb,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxb : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxb">; -// -// BUILTIN_INFO(HEXAGON.A2_vminub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminub">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxub,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxub : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxub">; -// -// BUILTIN_INFO(HEXAGON.A2_vminh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminh">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxh">; -// -// BUILTIN_INFO(HEXAGON.A2_vminuh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminuh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuh">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxuh,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxuh : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuh">; -// -// BUILTIN_INFO(HEXAGON.A2_vminw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminw">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxw">; -// -// BUILTIN_INFO(HEXAGON.A2_vminuw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vminuw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vminuw">; -// -// BUILTIN_INFO(HEXAGON.A2_vmaxuw,DI_ftype_DIDI,2) -// -def int_hexagon_A2_vmaxuw : -Hexagon_di_didi_Intrinsic<"HEXAGON_A2_vmaxuw">; -// -// BUILTIN_INFO(HEXAGON.A4_modwrapu,SI_ftype_SISI,2) -// -def int_hexagon_A4_modwrapu : -Hexagon_si_sisi_Intrinsic<"HEXAGON_A4_modwrapu">; -// -// BUILTIN_INFO(HEXAGON.F2_sfadd,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sfadd : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfadd">; -// -// BUILTIN_INFO(HEXAGON.F2_sfsub,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sfsub : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfsub">; -// -// BUILTIN_INFO(HEXAGON.F2_sfmpy,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sfmpy : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmpy">; -// -// BUILTIN_INFO(HEXAGON.F2_sffma,SF_ftype_SFSFSF,3) -// -def int_hexagon_F2_sffma : -Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma">; -// -// BUILTIN_INFO(HEXAGON.F2_sffma_sc,SF_ftype_SFSFSFQI,4) -// -def int_hexagon_F2_sffma_sc : -Hexagon_sf_sfsfsfqi_Intrinsic<"HEXAGON_F2_sffma_sc">; -// -// BUILTIN_INFO(HEXAGON.F2_sffms,SF_ftype_SFSFSF,3) -// -def int_hexagon_F2_sffms : -Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms">; -// -// BUILTIN_INFO(HEXAGON.F2_sffma_lib,SF_ftype_SFSFSF,3) -// -def int_hexagon_F2_sffma_lib : -Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffma_lib">; -// -// BUILTIN_INFO(HEXAGON.F2_sffms_lib,SF_ftype_SFSFSF,3) -// -def int_hexagon_F2_sffms_lib : -Hexagon_sf_sfsfsf_Intrinsic<"HEXAGON_F2_sffms_lib">; -// -// BUILTIN_INFO(HEXAGON.F2_sfcmpeq,QI_ftype_SFSF,2) -// -def int_hexagon_F2_sfcmpeq : -Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpeq">; -// -// BUILTIN_INFO(HEXAGON.F2_sfcmpgt,QI_ftype_SFSF,2) -// -def int_hexagon_F2_sfcmpgt : -Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpgt">; -// -// BUILTIN_INFO(HEXAGON.F2_sfcmpge,QI_ftype_SFSF,2) -// -def int_hexagon_F2_sfcmpge : -Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpge">; -// -// BUILTIN_INFO(HEXAGON.F2_sfcmpuo,QI_ftype_SFSF,2) -// -def int_hexagon_F2_sfcmpuo : -Hexagon_si_sfsf_Intrinsic<"HEXAGON_F2_sfcmpuo">; -// -// BUILTIN_INFO(HEXAGON.F2_sfmax,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sfmax : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmax">; -// -// BUILTIN_INFO(HEXAGON.F2_sfmin,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sfmin : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sfmin">; -// -// BUILTIN_INFO(HEXAGON.F2_sfclass,QI_ftype_SFSI,2) -// -def int_hexagon_F2_sfclass : -Hexagon_si_sfsi_Intrinsic<"HEXAGON_F2_sfclass">; -// -// BUILTIN_INFO(HEXAGON.F2_sfimm_p,SF_ftype_SI,1) -// -def int_hexagon_F2_sfimm_p : -Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_p">; -// -// BUILTIN_INFO(HEXAGON.F2_sfimm_n,SF_ftype_SI,1) -// -def int_hexagon_F2_sfimm_n : -Hexagon_sf_si_Intrinsic<"HEXAGON_F2_sfimm_n">; -// -// BUILTIN_INFO(HEXAGON.F2_sffixupn,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sffixupn : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupn">; -// -// BUILTIN_INFO(HEXAGON.F2_sffixupd,SF_ftype_SFSF,2) -// -def int_hexagon_F2_sffixupd : -Hexagon_sf_sfsf_Intrinsic<"HEXAGON_F2_sffixupd">; -// -// BUILTIN_INFO(HEXAGON.F2_sffixupr,SF_ftype_SF,1) -// -def int_hexagon_F2_sffixupr : -Hexagon_sf_sf_Intrinsic<"HEXAGON_F2_sffixupr">; -// -// BUILTIN_INFO(HEXAGON.F2_dfcmpeq,QI_ftype_DFDF,2) -// -def int_hexagon_F2_dfcmpeq : -Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpeq">; -// -// BUILTIN_INFO(HEXAGON.F2_dfcmpgt,QI_ftype_DFDF,2) -// -def int_hexagon_F2_dfcmpgt : -Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpgt">; -// -// BUILTIN_INFO(HEXAGON.F2_dfcmpge,QI_ftype_DFDF,2) -// -def int_hexagon_F2_dfcmpge : -Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpge">; -// -// BUILTIN_INFO(HEXAGON.F2_dfcmpuo,QI_ftype_DFDF,2) -// -def int_hexagon_F2_dfcmpuo : -Hexagon_si_dfdf_Intrinsic<"HEXAGON_F2_dfcmpuo">; -// -// BUILTIN_INFO(HEXAGON.F2_dfclass,QI_ftype_DFSI,2) -// -def int_hexagon_F2_dfclass : -Hexagon_si_dfsi_Intrinsic<"HEXAGON_F2_dfclass">; -// -// BUILTIN_INFO(HEXAGON.F2_dfimm_p,DF_ftype_SI,1) -// -def int_hexagon_F2_dfimm_p : -Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_p">; -// -// BUILTIN_INFO(HEXAGON.F2_dfimm_n,DF_ftype_SI,1) -// -def int_hexagon_F2_dfimm_n : -Hexagon_df_si_Intrinsic<"HEXAGON_F2_dfimm_n">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2df,DF_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2df : -Hexagon_df_sf_Intrinsic<"HEXAGON_F2_conv_sf2df">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2sf,SF_ftype_DF,1) -// -def int_hexagon_F2_conv_df2sf : -Hexagon_sf_df_Intrinsic<"HEXAGON_F2_conv_df2sf">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_uw2sf,SF_ftype_SI,1) -// -def int_hexagon_F2_conv_uw2sf : -Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_uw2sf">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_uw2df,DF_ftype_SI,1) -// -def int_hexagon_F2_conv_uw2df : -Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_uw2df">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_w2sf,SF_ftype_SI,1) -// -def int_hexagon_F2_conv_w2sf : -Hexagon_sf_si_Intrinsic<"HEXAGON_F2_conv_w2sf">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_w2df,DF_ftype_SI,1) -// -def int_hexagon_F2_conv_w2df : -Hexagon_df_si_Intrinsic<"HEXAGON_F2_conv_w2df">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_ud2sf,SF_ftype_DI,1) -// -def int_hexagon_F2_conv_ud2sf : -Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_ud2sf">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_ud2df,DF_ftype_DI,1) -// -def int_hexagon_F2_conv_ud2df : -Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_ud2df">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_d2sf,SF_ftype_DI,1) -// -def int_hexagon_F2_conv_d2sf : -Hexagon_sf_di_Intrinsic<"HEXAGON_F2_conv_d2sf">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_d2df,DF_ftype_DI,1) -// -def int_hexagon_F2_conv_d2df : -Hexagon_df_di_Intrinsic<"HEXAGON_F2_conv_d2df">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2uw,SI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2uw : -Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2w,SI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2w : -Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2ud,DI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2ud : -Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2d,DI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2d : -Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2uw,SI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2uw : -Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2w,SI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2w : -Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2ud,DI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2ud : -Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2d,DI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2d : -Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2uw_chop,SI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2uw_chop : -Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2w_chop,SI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2w_chop : -Hexagon_si_sf_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2ud_chop,DI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2ud_chop : -Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_sf2d_chop,DI_ftype_SF,1) -// -def int_hexagon_F2_conv_sf2d_chop : -Hexagon_di_sf_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2uw_chop,SI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2uw_chop : -Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2w_chop,SI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2w_chop : -Hexagon_si_df_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2ud_chop,DI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2ud_chop : -Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; -// -// BUILTIN_INFO(HEXAGON.F2_conv_df2d_chop,DI_ftype_DF,1) -// -def int_hexagon_F2_conv_df2d_chop : -Hexagon_di_df_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_asr_r_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_asl_r_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_lsr_r_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_r_r">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_lsl_r_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsl_r_r">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_r_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_p">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_r_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_p">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_r_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_p">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsl_r_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_p">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_r_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_r_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_r_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsl_r_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_r_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_r_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_r_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsl_r_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_r_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_r_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_r_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsl_r_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_r_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_r_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_r_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsl_r_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_r_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_r_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_r_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsl_r_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_r_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_r_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_r_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsl_r_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_r_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_r_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_r_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsl_r_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_r_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_r_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_r_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsl_r_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_p_xor,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_r_p_xor : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_p_xor,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_r_p_xor : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_p_xor,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_r_p_xor : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_p_xor,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsl_r_p_xor : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_r_sat,SI_ftype_SISI,2) -// -def int_hexagon_S2_asr_r_r_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_r_sat,SI_ftype_SISI,2) -// -def int_hexagon_S2_asl_r_r_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_asr_i_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_lsr_i_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_lsr_i_r">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_asl_i_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_i_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_p">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_i_p : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_p">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_i_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_i_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_acc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_i_r_acc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_i_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_i_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p_acc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_i_p_acc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_acc">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_i_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_i_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_nac,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_i_r_nac : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_i_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_i_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p_nac,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_i_p_nac : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_nac">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_xacc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_i_r_xacc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_xacc,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_i_r_xacc : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_xacc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_i_p_xacc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p_xacc,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_i_p_xacc : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_i_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_i_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_and,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_i_r_and : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asr_i_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asr_i_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_lsr_i_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_lsr_i_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_or,SI_ftype_SISISI,3) -// -def int_hexagon_S2_asl_i_r_or : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_asl_i_r_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_i_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_i_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p_and,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_i_p_and : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_and">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asr_i_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asr_i_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_lsr_i_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_lsr_i_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_p_or,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_asl_i_p_or : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_asl_i_p_or">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_r_sat,SI_ftype_SISI,2) -// -def int_hexagon_S2_asl_i_r_sat : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asl_i_r_sat">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd,SI_ftype_SISI,2) -// -def int_hexagon_S2_asr_i_r_rnd : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_r_rnd_goodsyntax,SI_ftype_SISI,2) -// -def int_hexagon_S2_asr_i_r_rnd_goodsyntax : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_p_rnd : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_p_rnd_goodsyntax,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_p_rnd_goodsyntax : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S4_lsli,SI_ftype_SISI,2) -// -def int_hexagon_S4_lsli : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_lsli">; -// -// BUILTIN_INFO(HEXAGON.S2_addasl_rrri,SI_ftype_SISISI,3) -// -def int_hexagon_S2_addasl_rrri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_addasl_rrri">; -// -// BUILTIN_INFO(HEXAGON.S4_andi_asl_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_andi_asl_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_ori_asl_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_ori_asl_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_addi_asl_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_addi_asl_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_subi_asl_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_subi_asl_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_andi_lsr_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_andi_lsr_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_andi_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_ori_lsr_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_ori_lsr_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_ori_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_addi_lsr_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_addi_lsr_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_addi_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.S4_subi_lsr_ri,SI_ftype_SISISI,3) -// -def int_hexagon_S4_subi_lsr_ri : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_subi_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.S2_valignib,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_valignib : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_valignib">; -// -// BUILTIN_INFO(HEXAGON.S2_valignrb,DI_ftype_DIDIQI,3) -// -def int_hexagon_S2_valignrb : -Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_valignrb">; -// -// BUILTIN_INFO(HEXAGON.S2_vspliceib,DI_ftype_DIDISI,3) -// -def int_hexagon_S2_vspliceib : -Hexagon_di_didisi_Intrinsic<"HEXAGON_S2_vspliceib">; -// -// BUILTIN_INFO(HEXAGON.S2_vsplicerb,DI_ftype_DIDIQI,3) -// -def int_hexagon_S2_vsplicerb : -Hexagon_di_didiqi_Intrinsic<"HEXAGON_S2_vsplicerb">; -// -// BUILTIN_INFO(HEXAGON.S2_vsplatrh,DI_ftype_SI,1) -// -def int_hexagon_S2_vsplatrh : -Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsplatrh">; -// -// BUILTIN_INFO(HEXAGON.S2_vsplatrb,SI_ftype_SI,1) -// -def int_hexagon_S2_vsplatrb : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_vsplatrb">; -// -// BUILTIN_INFO(HEXAGON.S2_insert,SI_ftype_SISISISI,4) -// -def int_hexagon_S2_insert : -Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_insert">; -// -// BUILTIN_INFO(HEXAGON.S2_tableidxb_goodsyntax,SI_ftype_SISISISI,4) -// -def int_hexagon_S2_tableidxb_goodsyntax : -Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S2_tableidxh_goodsyntax,SI_ftype_SISISISI,4) -// -def int_hexagon_S2_tableidxh_goodsyntax : -Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S2_tableidxw_goodsyntax,SI_ftype_SISISISI,4) -// -def int_hexagon_S2_tableidxw_goodsyntax : -Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S2_tableidxd_goodsyntax,SI_ftype_SISISISI,4) -// -def int_hexagon_S2_tableidxd_goodsyntax : -Hexagon_si_sisisisi_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.A4_bitspliti,DI_ftype_SISI,2) -// -def int_hexagon_A4_bitspliti : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitspliti">; -// -// BUILTIN_INFO(HEXAGON.A4_bitsplit,DI_ftype_SISI,2) -// -def int_hexagon_A4_bitsplit : -Hexagon_di_sisi_Intrinsic<"HEXAGON_A4_bitsplit">; -// -// BUILTIN_INFO(HEXAGON.S4_extract,SI_ftype_SISISI,3) -// -def int_hexagon_S4_extract : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S4_extract">; -// -// BUILTIN_INFO(HEXAGON.S2_extractu,SI_ftype_SISISI,3) -// -def int_hexagon_S2_extractu : -Hexagon_si_sisisi_Intrinsic<"HEXAGON_S2_extractu">; -// -// BUILTIN_INFO(HEXAGON.S2_insertp,DI_ftype_DIDISISI,4) -// -def int_hexagon_S2_insertp : -Hexagon_di_didisisi_Intrinsic<"HEXAGON_S2_insertp">; -// -// BUILTIN_INFO(HEXAGON.S4_extractp,DI_ftype_DISISI,3) -// -def int_hexagon_S4_extractp : -Hexagon_di_disisi_Intrinsic<"HEXAGON_S4_extractp">; -// -// BUILTIN_INFO(HEXAGON.S2_extractup,DI_ftype_DISISI,3) -// -def int_hexagon_S2_extractup : -Hexagon_di_disisi_Intrinsic<"HEXAGON_S2_extractup">; -// -// BUILTIN_INFO(HEXAGON.S2_insert_rp,SI_ftype_SISIDI,3) -// -def int_hexagon_S2_insert_rp : -Hexagon_si_sisidi_Intrinsic<"HEXAGON_S2_insert_rp">; -// -// BUILTIN_INFO(HEXAGON.S4_extract_rp,SI_ftype_SIDI,2) -// -def int_hexagon_S4_extract_rp : -Hexagon_si_sidi_Intrinsic<"HEXAGON_S4_extract_rp">; -// -// BUILTIN_INFO(HEXAGON.S2_extractu_rp,SI_ftype_SIDI,2) -// -def int_hexagon_S2_extractu_rp : -Hexagon_si_sidi_Intrinsic<"HEXAGON_S2_extractu_rp">; -// -// BUILTIN_INFO(HEXAGON.S2_insertp_rp,DI_ftype_DIDIDI,3) -// -def int_hexagon_S2_insertp_rp : -Hexagon_di_dididi_Intrinsic<"HEXAGON_S2_insertp_rp">; -// -// BUILTIN_INFO(HEXAGON.S4_extractp_rp,DI_ftype_DIDI,2) -// -def int_hexagon_S4_extractp_rp : -Hexagon_di_didi_Intrinsic<"HEXAGON_S4_extractp_rp">; -// -// BUILTIN_INFO(HEXAGON.S2_extractup_rp,DI_ftype_DIDI,2) -// -def int_hexagon_S2_extractup_rp : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_extractup_rp">; -// -// BUILTIN_INFO(HEXAGON.S2_tstbit_i,QI_ftype_SISI,2) -// -def int_hexagon_S2_tstbit_i : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_i">; -// -// BUILTIN_INFO(HEXAGON.S4_ntstbit_i,QI_ftype_SISI,2) -// -def int_hexagon_S4_ntstbit_i : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_i">; -// -// BUILTIN_INFO(HEXAGON.S2_setbit_i,SI_ftype_SISI,2) -// -def int_hexagon_S2_setbit_i : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_i">; -// -// BUILTIN_INFO(HEXAGON.S2_togglebit_i,SI_ftype_SISI,2) -// -def int_hexagon_S2_togglebit_i : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_i">; -// -// BUILTIN_INFO(HEXAGON.S2_clrbit_i,SI_ftype_SISI,2) -// -def int_hexagon_S2_clrbit_i : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_i">; -// -// BUILTIN_INFO(HEXAGON.S2_tstbit_r,QI_ftype_SISI,2) -// -def int_hexagon_S2_tstbit_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_tstbit_r">; -// -// BUILTIN_INFO(HEXAGON.S4_ntstbit_r,QI_ftype_SISI,2) -// -def int_hexagon_S4_ntstbit_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_ntstbit_r">; -// -// BUILTIN_INFO(HEXAGON.S2_setbit_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_setbit_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_setbit_r">; -// -// BUILTIN_INFO(HEXAGON.S2_togglebit_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_togglebit_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_togglebit_r">; -// -// BUILTIN_INFO(HEXAGON.S2_clrbit_r,SI_ftype_SISI,2) -// -def int_hexagon_S2_clrbit_r : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S2_clrbit_r">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_i_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_i_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_r_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vh">; -// -// BUILTIN_INFO(HEXAGON.S5_asrhub_rnd_sat_goodsyntax,SI_ftype_DISI,2) -// -def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : -Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S5_asrhub_sat,SI_ftype_DISI,2) -// -def int_hexagon_S5_asrhub_sat : -Hexagon_si_disi_Intrinsic<"HEXAGON_S5_asrhub_sat">; -// -// BUILTIN_INFO(HEXAGON.S5_vasrhrnd_goodsyntax,DI_ftype_DISI,2) -// -def int_hexagon_S5_vasrhrnd_goodsyntax : -Hexagon_di_disi_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_r_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_r_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_vh,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsl_r_vh : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vh">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_i_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_i_svw_trun,SI_ftype_DISI,2) -// -def int_hexagon_S2_asr_i_svw_trun : -Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_svw_trun,SI_ftype_DISI,2) -// -def int_hexagon_S2_asr_r_svw_trun : -Hexagon_si_disi_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_i_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_i_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_i_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_i_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_i_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_i_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_asr_r_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_asr_r_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asr_r_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_asl_r_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_asl_r_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_asl_r_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_lsr_r_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsr_r_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsr_r_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_lsl_r_vw,DI_ftype_DISI,2) -// -def int_hexagon_S2_lsl_r_vw : -Hexagon_di_disi_Intrinsic<"HEXAGON_S2_lsl_r_vw">; -// -// BUILTIN_INFO(HEXAGON.S2_vrndpackwh,SI_ftype_DI,1) -// -def int_hexagon_S2_vrndpackwh : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwh">; -// -// BUILTIN_INFO(HEXAGON.S2_vrndpackwhs,SI_ftype_DI,1) -// -def int_hexagon_S2_vrndpackwhs : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vrndpackwhs">; -// -// BUILTIN_INFO(HEXAGON.S2_vsxtbh,DI_ftype_SI,1) -// -def int_hexagon_S2_vsxtbh : -Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxtbh">; -// -// BUILTIN_INFO(HEXAGON.S2_vzxtbh,DI_ftype_SI,1) -// -def int_hexagon_S2_vzxtbh : -Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxtbh">; -// -// BUILTIN_INFO(HEXAGON.S2_vsathub,SI_ftype_DI,1) -// -def int_hexagon_S2_vsathub : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathub">; -// -// BUILTIN_INFO(HEXAGON.S2_svsathub,SI_ftype_SI,1) -// -def int_hexagon_S2_svsathub : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathub">; -// -// BUILTIN_INFO(HEXAGON.S2_svsathb,SI_ftype_SI,1) -// -def int_hexagon_S2_svsathb : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_svsathb">; -// -// BUILTIN_INFO(HEXAGON.S2_vsathb,SI_ftype_DI,1) -// -def int_hexagon_S2_vsathb : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsathb">; -// -// BUILTIN_INFO(HEXAGON.S2_vtrunohb,SI_ftype_DI,1) -// -def int_hexagon_S2_vtrunohb : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunohb">; -// -// BUILTIN_INFO(HEXAGON.S2_vtrunewh,DI_ftype_DIDI,2) -// -def int_hexagon_S2_vtrunewh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunewh">; -// -// BUILTIN_INFO(HEXAGON.S2_vtrunowh,DI_ftype_DIDI,2) -// -def int_hexagon_S2_vtrunowh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_vtrunowh">; -// -// BUILTIN_INFO(HEXAGON.S2_vtrunehb,SI_ftype_DI,1) -// -def int_hexagon_S2_vtrunehb : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vtrunehb">; -// -// BUILTIN_INFO(HEXAGON.S2_vsxthw,DI_ftype_SI,1) -// -def int_hexagon_S2_vsxthw : -Hexagon_di_si_Intrinsic<"HEXAGON_S2_vsxthw">; -// -// BUILTIN_INFO(HEXAGON.S2_vzxthw,DI_ftype_SI,1) -// -def int_hexagon_S2_vzxthw : -Hexagon_di_si_Intrinsic<"HEXAGON_S2_vzxthw">; -// -// BUILTIN_INFO(HEXAGON.S2_vsatwh,SI_ftype_DI,1) -// -def int_hexagon_S2_vsatwh : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwh">; -// -// BUILTIN_INFO(HEXAGON.S2_vsatwuh,SI_ftype_DI,1) -// -def int_hexagon_S2_vsatwuh : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_vsatwuh">; -// -// BUILTIN_INFO(HEXAGON.S2_packhl,DI_ftype_SISI,2) -// -def int_hexagon_S2_packhl : -Hexagon_di_sisi_Intrinsic<"HEXAGON_S2_packhl">; -// -// BUILTIN_INFO(HEXAGON.A2_swiz,SI_ftype_SI,1) -// -def int_hexagon_A2_swiz : -Hexagon_si_si_Intrinsic<"HEXAGON_A2_swiz">; -// -// BUILTIN_INFO(HEXAGON.S2_vsathub_nopack,DI_ftype_DI,1) -// -def int_hexagon_S2_vsathub_nopack : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathub_nopack">; -// -// BUILTIN_INFO(HEXAGON.S2_vsathb_nopack,DI_ftype_DI,1) -// -def int_hexagon_S2_vsathb_nopack : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsathb_nopack">; -// -// BUILTIN_INFO(HEXAGON.S2_vsatwh_nopack,DI_ftype_DI,1) -// -def int_hexagon_S2_vsatwh_nopack : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; -// -// BUILTIN_INFO(HEXAGON.S2_vsatwuh_nopack,DI_ftype_DI,1) -// -def int_hexagon_S2_vsatwuh_nopack : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; -// -// BUILTIN_INFO(HEXAGON.S2_shuffob,DI_ftype_DIDI,2) -// -def int_hexagon_S2_shuffob : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffob">; -// -// BUILTIN_INFO(HEXAGON.S2_shuffeb,DI_ftype_DIDI,2) -// -def int_hexagon_S2_shuffeb : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeb">; -// -// BUILTIN_INFO(HEXAGON.S2_shuffoh,DI_ftype_DIDI,2) -// -def int_hexagon_S2_shuffoh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffoh">; -// -// BUILTIN_INFO(HEXAGON.S2_shuffeh,DI_ftype_DIDI,2) -// -def int_hexagon_S2_shuffeh : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_shuffeh">; -// -// BUILTIN_INFO(HEXAGON.S5_popcountp,SI_ftype_DI,1) -// -def int_hexagon_S5_popcountp : -Hexagon_si_di_Intrinsic<"HEXAGON_S5_popcountp">; -// -// BUILTIN_INFO(HEXAGON.S4_parity,SI_ftype_SISI,2) -// -def int_hexagon_S4_parity : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_parity">; -// -// BUILTIN_INFO(HEXAGON.S2_parityp,SI_ftype_DIDI,2) -// -def int_hexagon_S2_parityp : -Hexagon_si_didi_Intrinsic<"HEXAGON_S2_parityp">; -// -// BUILTIN_INFO(HEXAGON.S2_lfsp,DI_ftype_DIDI,2) -// -def int_hexagon_S2_lfsp : -Hexagon_di_didi_Intrinsic<"HEXAGON_S2_lfsp">; -// -// BUILTIN_INFO(HEXAGON.S2_clbnorm,SI_ftype_SI,1) -// -def int_hexagon_S2_clbnorm : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_clbnorm">; -// -// BUILTIN_INFO(HEXAGON.S4_clbaddi,SI_ftype_SISI,2) -// -def int_hexagon_S4_clbaddi : -Hexagon_si_sisi_Intrinsic<"HEXAGON_S4_clbaddi">; -// -// BUILTIN_INFO(HEXAGON.S4_clbpnorm,SI_ftype_DI,1) -// -def int_hexagon_S4_clbpnorm : -Hexagon_si_di_Intrinsic<"HEXAGON_S4_clbpnorm">; -// -// BUILTIN_INFO(HEXAGON.S4_clbpaddi,SI_ftype_DISI,2) -// -def int_hexagon_S4_clbpaddi : -Hexagon_si_disi_Intrinsic<"HEXAGON_S4_clbpaddi">; -// -// BUILTIN_INFO(HEXAGON.S2_clb,SI_ftype_SI,1) -// -def int_hexagon_S2_clb : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_clb">; -// -// BUILTIN_INFO(HEXAGON.S2_cl0,SI_ftype_SI,1) -// -def int_hexagon_S2_cl0 : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl0">; -// -// BUILTIN_INFO(HEXAGON.S2_cl1,SI_ftype_SI,1) -// -def int_hexagon_S2_cl1 : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_cl1">; -// -// BUILTIN_INFO(HEXAGON.S2_clbp,SI_ftype_DI,1) -// -def int_hexagon_S2_clbp : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_clbp">; -// -// BUILTIN_INFO(HEXAGON.S2_cl0p,SI_ftype_DI,1) -// -def int_hexagon_S2_cl0p : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl0p">; -// -// BUILTIN_INFO(HEXAGON.S2_cl1p,SI_ftype_DI,1) -// -def int_hexagon_S2_cl1p : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_cl1p">; -// -// BUILTIN_INFO(HEXAGON.S2_brev,SI_ftype_SI,1) -// -def int_hexagon_S2_brev : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_brev">; -// -// BUILTIN_INFO(HEXAGON.S2_brevp,DI_ftype_DI,1) -// -def int_hexagon_S2_brevp : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_brevp">; -// -// BUILTIN_INFO(HEXAGON.S2_ct0,SI_ftype_SI,1) -// -def int_hexagon_S2_ct0 : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct0">; -// -// BUILTIN_INFO(HEXAGON.S2_ct1,SI_ftype_SI,1) -// -def int_hexagon_S2_ct1 : -Hexagon_si_si_Intrinsic<"HEXAGON_S2_ct1">; -// -// BUILTIN_INFO(HEXAGON.S2_ct0p,SI_ftype_DI,1) -// -def int_hexagon_S2_ct0p : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct0p">; -// -// BUILTIN_INFO(HEXAGON.S2_ct1p,SI_ftype_DI,1) -// -def int_hexagon_S2_ct1p : -Hexagon_si_di_Intrinsic<"HEXAGON_S2_ct1p">; -// -// BUILTIN_INFO(HEXAGON.S2_interleave,DI_ftype_DI,1) -// -def int_hexagon_S2_interleave : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_interleave">; -// -// BUILTIN_INFO(HEXAGON.S2_deinterleave,DI_ftype_DI,1) -// -def int_hexagon_S2_deinterleave : -Hexagon_di_di_Intrinsic<"HEXAGON_S2_deinterleave">; - // // BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1) // @@ -4934,6042 +160,6139 @@ def int_hexagon_S4_stored_locked : Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty], [llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>; -// V60 +def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy", + [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], + [IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>]>; -class Hexagon_v2048v2048_Intrinsic_T<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty], - [IntrNoMem]>; - -// tag : V6_hi_W -// tag : V6_lo_W -class Hexagon_v512v1024_Intrinsic_T<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v32i32_ty], - [IntrNoMem]>; - -// tag : V6_hi_W_128B -// tag : V6_lo_W_128B -class Hexagon_v1024v2048_Intrinsic_T<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v64i32_ty], - [IntrNoMem]>; - -class Hexagon_v1024v1024_Intrinsic_T<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset", + [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], + [IntrArgMemOnly, NoCapture<0>, WriteOnly<0>]>; -// BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1) -// tag : V6_hi -def int_hexagon_V6_hi : -Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_hi">; +multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { + def NAME#_pci : Hexagon_NonGCC_Intrinsic< + [ElTy, llvm_ptr_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], + [IntrArgMemOnly, NoCapture<3>]>; + def NAME#_pcr : Hexagon_NonGCC_Intrinsic< + [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], + [IntrArgMemOnly, NoCapture<2>]>; +} -// BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1) -// tag : V6_lo -def int_hexagon_V6_lo : -Hexagon_v512v1024_Intrinsic_T<"HEXAGON_V6_lo">; +defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; +defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; +defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; +defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; +defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; +defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; -// BUILTIN_INFO(HEXAGON.V6_hi_W,VI_ftype_VI,1) -// tag : V6_hi_128B -def int_hexagon_V6_hi_128B : -Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_hi_128B">; +multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { + def NAME#_pci : Hexagon_NonGCC_Intrinsic< + [llvm_ptr_ty], + [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], + [IntrArgMemOnly, NoCapture<4>]>; + def NAME#_pcr : Hexagon_NonGCC_Intrinsic< + [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], + [IntrArgMemOnly, NoCapture<3>]>; +} -// BUILTIN_INFO(HEXAGON.V6_lo_W,VI_ftype_VI,1) -// tag : V6_lo_128B -def int_hexagon_V6_lo_128B : -Hexagon_v1024v2048_Intrinsic_T<"HEXAGON_V6_lo_128B">; +defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; +defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; +defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; +defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; +defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; -// BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1) -// tag : V6_vassignp -def int_hexagon_V6_vassignp : -Hexagon_v1024v1024_Intrinsic_T<"HEXAGON_V6_vassignp">; +// The front-end emits the intrinsic call with only two arguments. The third +// argument from the builtin is already used by front-end to write to memory +// by generating a store. +class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> + : Hexagon_NonGCC_Intrinsic< + [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], + [IntrReadMem]>; -// BUILTIN_INFO(HEXAGON.V6_vassignp,VI_ftype_VI,1) -// tag : V6_vassignp_128B -def int_hexagon_V6_vassignp_128B : -Hexagon_v2048v2048_Intrinsic_T<"HEXAGON_V6_vassignp_128B">; +def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; +def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; +def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; +def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; +def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; +def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; +def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; +def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; +def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; +def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; +def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; // -// Hexagon_iii_Intrinsic<string GCCIntSuffix> -// tag : S6_rol_i_r -class Hexagon_iii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; - +// Masked vector stores // -// Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix> -// tag : S6_rol_i_p -class Hexagon_LLiLLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; // -// Hexagon_iiii_Intrinsic<string GCCIntSuffix> -// tag : S6_rol_i_r_acc -class Hexagon_iiii_Intrinsic<string GCCIntSuffix> +// Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> +// tag: V6_vS32b_qpred_ai +class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty], + [IntrArgMemOnly]>; // -// Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix> -// tag : S6_rol_i_p_acc -class Hexagon_LLiLLiLLii_Intrinsic<string GCCIntSuffix> +// Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> +// tag: V6_vS32b_qpred_ai_128B +class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_valignb -class Hexagon_v512v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_qpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">; -// -// Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_valignb_128B -class Hexagon_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nqpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">; -// -// Hexagon_v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vror -class Hexagon_v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nt_qpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">; -// -// Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vror_128B -class Hexagon_v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nt_nqpred_ai : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">; -// -// Hexagon_v1024v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vunpackub -class Hexagon_v1024v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_qpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">; -// -// Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vunpackub_128B -class Hexagon_v2048v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nqpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">; -// -// Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vunpackob -class Hexagon_v1024v1024v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nt_qpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">; -// -// Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vunpackob_128B -class Hexagon_v2048v2048v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">; -// -// Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vpackeb -class Hexagon_v512v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstoreq : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">; -// -// Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vpackeb_128B -class Hexagon_v1024v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorenq : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">; -// -// Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpybus_dv_128B -class Hexagon_v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorentq : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">; -// -// Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpybus_dv_acc_128B -class Hexagon_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorentnq : +Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">; -// -// Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhvsat_acc -class Hexagon_v512v512v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstoreq_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">; -// -// Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhvsat_acc_128B -class Hexagon_v1024v1024v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorenq_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">; -// -// Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhisat -class Hexagon_v512v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorentq_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">; -// -// Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhisat_128B -class Hexagon_v1024v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmaskedstorentnq_128B : +Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">; -// -// Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhisat_acc -class Hexagon_v512v512v1024i_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v16i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vdmpyhisat_acc_128B -class Hexagon_v1024v1024v2048i_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyubi -class Hexagon_v1024v1024ii_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, + llvm_v64i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyubi_128B -class Hexagon_v2048v2048ii_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v16i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyubi_acc -class Hexagon_v1024v1024v1024ii_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyubi_acc_128B -class Hexagon_v2048v2048v2048ii_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddb_dv_128B -class Hexagon_v2048v2048v2048_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], - [IntrNoMem]>; + [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v64i32_ty], + [IntrArgMemOnly]>; -// -// Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddubh -class Hexagon_v1024v512v512_Intrinsic<string GCCIntSuffix> +def int_hexagon_V6_vgathermw : +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">; + +def int_hexagon_V6_vgathermw_128B : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">; + +def int_hexagon_V6_vgathermh : +Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">; + +def int_hexagon_V6_vgathermh_128B : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">; + +def int_hexagon_V6_vgathermhw : +Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">; + +def int_hexagon_V6_vgathermhw_128B : +Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">; + +def int_hexagon_V6_vgathermwq : +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">; + +def int_hexagon_V6_vgathermwq_128B : +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">; + +def int_hexagon_V6_vgathermhq : +Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">; + +def int_hexagon_V6_vgathermhq_128B : +Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">; + +def int_hexagon_V6_vgathermhwq : +Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">; + +def int_hexagon_V6_vgathermhwq_128B : +Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">; + +class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v16i32_ty,llvm_v16i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddubh_128B -class Hexagon_v2048v1024v1024_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty,llvm_v32i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vd0 -class Hexagon_v512_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [], - [IntrNoMem]>; + [], [llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v16i32_ty, + llvm_v16i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vd0_128B -class Hexagon_v1024_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [], - [IntrNoMem]>; + [], [llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty, + llvm_v32i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddbq -class Hexagon_v512v64iv512v512_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v32i32_ty,llvm_v16i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddbq_128B -class Hexagon_v1024v128iv1024v1024_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; + [], [llvm_i32_ty,llvm_i32_ty, + llvm_v64i32_ty,llvm_v32i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vabsh -class Hexagon_v512v512_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty], - [IntrNoMem]>; + [], [llvm_v512i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v32i32_ty, + llvm_v16i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vabsh_128B -class Hexagon_v1024v1024_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty], - [IntrNoMem]>; + [], [llvm_v1024i1_ty,llvm_i32_ty, + llvm_i32_ty,llvm_v64i32_ty, + llvm_v32i32_ty], + [IntrWriteMem]>; -// -// Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpybv_acc -class Hexagon_v1024v1024v512v512_Intrinsic<string GCCIntSuffix> +class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix> : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [llvm_v64i32_ty], [], [IntrNoMem]>; // -// Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpybv_acc_128B -class Hexagon_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw +def int_hexagon_V6_vscattermw : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">; // -// Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyub -class Hexagon_v1024v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_128B +def int_hexagon_V6_vscattermw_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">; // -// Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyub_128B -class Hexagon_v2048v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh +def int_hexagon_V6_vscattermh : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">; // -// Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyub_acc -class Hexagon_v1024v1024v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_128B +def int_hexagon_V6_vscattermh_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">; // -// Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyub_acc_128B -class Hexagon_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_add +def int_hexagon_V6_vscattermw_add : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">; // -// Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandqrt -class Hexagon_v512v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermw_add_128B +def int_hexagon_V6_vscattermw_add_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">; // -// Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandqrt_128B -class Hexagon_v1024v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_add +def int_hexagon_V6_vscattermh_add : +Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">; // -// Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandqrt_acc -class Hexagon_v512v512v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4) +// tag : V6_vscattermh_add_128B +def int_hexagon_V6_vscattermh_add_128B : +Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">; // -// Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandqrt_acc_128B -class Hexagon_v1024v1024v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermwq +def int_hexagon_V6_vscattermwq : +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">; // -// Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvrt -class Hexagon_v64iv512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermwq_128B +def int_hexagon_V6_vscattermwq_128B : +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">; // -// Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvrt_128B -class Hexagon_v128iv1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermhq +def int_hexagon_V6_vscattermhq : +Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">; // -// Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvrt_acc -class Hexagon_v64iv64iv512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5) +// tag : V6_vscattermhq_128B +def int_hexagon_V6_vscattermhq_128B : +Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">; // -// Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvrt_acc_128B -class Hexagon_v128iv128iv1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw +def int_hexagon_V6_vscattermhw : +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">; // -// Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vgtw -class Hexagon_v64iv512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_128B +def int_hexagon_V6_vscattermhw_128B : +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">; // -// Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vgtw_128B -class Hexagon_v128iv1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5) +// tag : V6_vscattermhwq +def int_hexagon_V6_vscattermhwq : +Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">; // -// Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vgtw_and -class Hexagon_v64iv64iv512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5) +// tag : V6_vscattermhwq_128B +def int_hexagon_V6_vscattermhwq_128B : +Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">; // -// Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vgtw_and_128B -class Hexagon_v128iv128iv1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_add +def int_hexagon_V6_vscattermhw_add : +Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">; // -// Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix> +// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4) +// tag : V6_vscattermhw_add_128B +def int_hexagon_V6_vscattermhw_add_128B : +Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">; + +// Auto-generated intrinsics + +// tag : S2_vsatwh +class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybusv +class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybusv +class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : V6_vaslw_acc +class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vaslw_acc +class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vmux +class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vmux +class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : S2_tableidxd_goodsyntax +class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vandnqrt_acc +class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vandnqrt_acc +class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybusi +class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybusi +class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vsubb_dv +class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], + [IntrNoMem]>; + +// tag : M2_mpysu_up +class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : M2_mpyud_acc_ll_s0 +class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : S2_lsr_i_r_nac +class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : M2_cmpysc_s0 +class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : S2_shuffoh +class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : F2_sfmax +class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_float_ty,llvm_float_ty], + [IntrNoMem, Throws]>; + +// tag : A2_vabswsat +class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty], + [IntrNoMem]>; + +// tag : +class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : V6_ldnp0 +class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_ldnp0 +class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vdmpyhb +class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vdmpyhb +class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : A4_vcmphgti +class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : +class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : S6_rol_i_p_or +class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vgtuh_and +class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vgtuh_and +class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : A2_abssat +class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + +// tag : A2_vcmpwgtu +class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vtmpybus_acc +class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : F2_conv_df2uw_chop +class Hexagon_i32_double_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_double_ty], + [IntrNoMem]>; + // tag : V6_pred_or -class Hexagon_v64iv64iv64i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty], - [IntrNoMem]>; +class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty], + [IntrNoMem]>; -// -// Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_or_128B -class Hexagon_v128iv128iv128i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty], - [IntrNoMem]>; +// tag : V6_pred_or +class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty], + [IntrNoMem]>; -// -// Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_not -class Hexagon_v64iv64i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v512i1_ty], - [IntrNoMem]>; +// tag : S2_asr_i_p_rnd_goodsyntax +class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_not_128B -class Hexagon_v128iv128i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v1024i1_ty], - [IntrNoMem]>; +// tag : F2_conv_w2df +class Hexagon_double_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_double_ty], [llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_scalar2 -class Hexagon_v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_vunpackuh +class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty], + [IntrNoMem]>; -// -// Hexagon_v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_scalar2_128B -class Hexagon_v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_vunpackuh +class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty], + [IntrNoMem]>; -// -// Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vswap -class Hexagon_v1024v64iv512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +// tag : V6_vadduhw_acc +class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; -// -// Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vswap_128B -class Hexagon_v2048v128iv1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +// tag : V6_vadduhw_acc +class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; -// -// Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vshuffvdd -class Hexagon_v1024v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// tag : M2_vdmacs_s0 +class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; -// -// Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vshuffvdd_128B -class Hexagon_v2048v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_vrmpybub_rtt_acc +class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybub_rtt_acc +class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; +// tag : V6_ldu0 +class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_ldu0 +class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_i32_ty], + [IntrNoMem]>; + +// tag : S4_extract_rp +class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vdmpyhsuisat +class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vdmpyhsuisat +class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : A2_addsp +class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], + [IntrNoMem]>; -// -// Hexagon_iv512i_Intrinsic<string GCCIntSuffix> // tag : V6_extractw -class Hexagon_iv512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_iv1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_extractw_128B -class Hexagon_iv1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_extractw +class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_lvsplatw -class Hexagon_v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_lo +class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v32i32_ty], + [IntrNoMem]>; -// -// Hexagon_v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_lvsplatw_128B -class Hexagon_v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_lo +class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v64i32_ty], + [IntrNoMem]>; + +// tag : V6_vlutvwhi +class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vlutvwhi +class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vgtuh +class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vgtuh +class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : F2_sffma_lib +class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], + [IntrNoMem, Throws]>; + +// tag : F2_conv_ud2df +class Hexagon_double_i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_double_ty], [llvm_i64_ty], + [IntrNoMem]>; + +// tag : S2_vzxthw +class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vtmpyhb +class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vshufoeh +class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vshufoeh +class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : V6_vlut4 +class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vlut4 +class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : +class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : F2_conv_uw2sf +class Hexagon_float_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vswap +class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vswap +class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : V6_vandnqrt +class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vandnqrt +class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vmpyub +class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : A5_ACS +class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vunpackob +class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vunpackob +class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : V6_vmpyhsat_acc +class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vmpyhsat_acc +class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix> // tag : V6_vlutvvb_oracc -class Hexagon_v512v512v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvvb_oracc_128B -class Hexagon_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_vlutvvb_oracc +class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybub_rtt +class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vrmpybub_rtt +class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : A4_addp_c +class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vrsadubi_acc +class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vrsadubi_acc +class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : F2_conv_df2sf +class Hexagon_float_double_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_double_ty], + [IntrNoMem]>; + +// tag : V6_vandvqv +class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vandvqv +class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : C2_vmux +class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : F2_sfcmpeq +class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], + [IntrNoMem, Throws]>; + +// tag : V6_vmpahhsat +class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vmpahhsat +class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], + [IntrNoMem]>; + +// tag : V6_vandvrt +class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vandvrt +class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vsubcarry +class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic + : Hexagon_NonGCC_Intrinsic< + [llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty], + [IntrNoMem]>; + +// tag : V6_vsubcarry +class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B + : Hexagon_NonGCC_Intrinsic< + [llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty], + [IntrNoMem]>; + +// tag : F2_sffixupr +class Hexagon_float_float_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_float_ty], + [IntrNoMem, Throws]>; + +// tag : V6_vandvrt_acc +class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vandvrt_acc +class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vmpyowh_sacc +class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], + [IntrNoMem]>; + +// tag : V6_vmpyowh_sacc +class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], + [IntrNoMem]>; + +// tag : S2_insertp +class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : F2_sfinvsqrta +class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty,llvm_i32_ty], [llvm_float_ty], + [IntrNoMem, Throws]>; + +// tag : V6_vtran2x2_map +class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; + +// tag : V6_vtran2x2_map +class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix> // tag : V6_vlutvwh_oracc -class Hexagon_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvwh_oracc_128B -class Hexagon_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +// tag : V6_vlutvwh_oracc +class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> -// tag: V6_vS32b_qpred_ai -class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty], - [IntrArgMemOnly]>; +// tag : F2_dfcmpge +class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], + [IntrNoMem, Throws]>; -// -// Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> -// tag: V6_vS32b_qpred_ai_128B -class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty], - [IntrArgMemOnly]>; +// tag : F2_conv_df2d_chop +class Hexagon_i64_double_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_double_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r,SI_ftype_SISI,2) -// tag : S6_rol_i_r -def int_hexagon_S6_rol_i_r : -Hexagon_iii_Intrinsic<"HEXAGON_S6_rol_i_r">; +// tag : F2_conv_sf2w +class Hexagon_i32_float_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_float_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p,DI_ftype_DISI,2) -// tag : S6_rol_i_p -def int_hexagon_S6_rol_i_p : -Hexagon_LLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p">; +// tag : F2_sfclass +class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], + [IntrNoMem, Throws]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r_acc,SI_ftype_SISISI,3) -// tag : S6_rol_i_r_acc -def int_hexagon_S6_rol_i_r_acc : -Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_acc">; +// tag : F2_conv_sf2ud_chop +class Hexagon_i64_float_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty], [llvm_float_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p_acc,DI_ftype_DIDISI,3) -// tag : S6_rol_i_p_acc -def int_hexagon_S6_rol_i_p_acc : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_acc">; +// tag : V6_pred_scalar2v2 +class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_i32_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r_nac,SI_ftype_SISISI,3) -// tag : S6_rol_i_r_nac -def int_hexagon_S6_rol_i_r_nac : -Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_nac">; +// tag : V6_pred_scalar2v2 +class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_i32_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p_nac,DI_ftype_DIDISI,3) -// tag : S6_rol_i_p_nac -def int_hexagon_S6_rol_i_p_nac : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_nac">; +// tag : F2_sfrecipa +class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty], + [IntrNoMem, Throws]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r_xacc,SI_ftype_SISISI,3) -// tag : S6_rol_i_r_xacc -def int_hexagon_S6_rol_i_r_xacc : -Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">; +// tag : V6_vprefixqh +class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v512i1_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p_xacc,DI_ftype_DIDISI,3) -// tag : S6_rol_i_p_xacc -def int_hexagon_S6_rol_i_p_xacc : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">; +// tag : V6_vprefixqh +class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v1024i1_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r_and,SI_ftype_SISISI,3) -// tag : S6_rol_i_r_and -def int_hexagon_S6_rol_i_r_and : -Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_and">; +// tag : V6_vdmpyhisat_acc +class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_r_or,SI_ftype_SISISI,3) -// tag : S6_rol_i_r_or -def int_hexagon_S6_rol_i_r_or : -Hexagon_iiii_Intrinsic<"HEXAGON_S6_rol_i_r_or">; +// tag : V6_vdmpyhisat_acc +class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p_and,DI_ftype_DIDISI,3) -// tag : S6_rol_i_p_and -def int_hexagon_S6_rol_i_p_and : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_and">; +// tag : F2_conv_ud2sf +class Hexagon_float_i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_i64_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S6_rol_i_p_or,DI_ftype_DIDISI,3) -// tag : S6_rol_i_p_or -def int_hexagon_S6_rol_i_p_or : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S6_rol_i_p_or">; +// tag : F2_conv_sf2df +class Hexagon_double_float_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_double_ty], [llvm_float_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.S2_cabacencbin,DI_ftype_DIDIQI,3) -// tag : S2_cabacencbin -def int_hexagon_S2_cabacencbin : -Hexagon_LLiLLiLLii_Intrinsic<"HEXAGON_S2_cabacencbin">; +// tag : F2_sffma_sc +class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], + [IntrNoMem, Throws]>; -// -// BUILTIN_INFO(HEXAGON.V6_valignb,VI_ftype_VIVISI,3) -// tag : V6_valignb -def int_hexagon_V6_valignb : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignb">; +// tag : F2_dfclass +class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], + [IntrNoMem, Throws]>; -// -// BUILTIN_INFO(HEXAGON.V6_valignb_128B,VI_ftype_VIVISI,3) -// tag : V6_valignb_128B -def int_hexagon_V6_valignb_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignb_128B">; +// tag : V6_vd0 +class Hexagon_v16i32__Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v16i32_ty], [], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vlalignb,VI_ftype_VIVISI,3) -// tag : V6_vlalignb -def int_hexagon_V6_vlalignb : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignb">; +// tag : V6_vd0 +class Hexagon_v32i32__Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v32i32_ty], [], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vlalignb_128B,VI_ftype_VIVISI,3) -// tag : V6_vlalignb_128B -def int_hexagon_V6_vlalignb_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignb_128B">; +// tag : V6_vdd0 +class Hexagon_v64i32__Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_valignbi,VI_ftype_VIVISI,3) -// tag : V6_valignbi -def int_hexagon_V6_valignbi : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_valignbi">; +// tag : S2_insert_rp +class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_valignbi_128B,VI_ftype_VIVISI,3) -// tag : V6_valignbi_128B -def int_hexagon_V6_valignbi_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_valignbi_128B">; +// tag : V6_vassignp +class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v64i32_ty], [llvm_v64i32_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vlalignbi,VI_ftype_VIVISI,3) -// tag : V6_vlalignbi -def int_hexagon_V6_vlalignbi : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlalignbi">; +// tag : A6_vminub_RdP +class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vlalignbi_128B,VI_ftype_VIVISI,3) -// tag : V6_vlalignbi_128B -def int_hexagon_V6_vlalignbi_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlalignbi_128B">; +// tag : V6_pred_not +class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v512i1_ty], [llvm_v512i1_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vror,VI_ftype_VISI,2) -// tag : V6_vror -def int_hexagon_V6_vror : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vror">; +// tag : V6_pred_not +class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix> + : Hexagon_Intrinsic<GCCIntSuffix, + [llvm_v1024i1_ty], [llvm_v1024i1_ty], + [IntrNoMem]>; -// -// BUILTIN_INFO(HEXAGON.V6_vror_128B,VI_ftype_VISI,2) -// tag : V6_vror_128B -def int_hexagon_V6_vror_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vror_128B">; +// V5 Scalar Instructions. -// -// BUILTIN_INFO(HEXAGON.V6_vunpackub,VD_ftype_VI,1) -// tag : V6_vunpackub -def int_hexagon_V6_vunpackub : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackub">; +def int_hexagon_S2_asr_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackub_128B,VD_ftype_VI,1) -// tag : V6_vunpackub_128B -def int_hexagon_V6_vunpackub_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackub_128B">; +def int_hexagon_S2_vsatwh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackb,VD_ftype_VI,1) -// tag : V6_vunpackb -def int_hexagon_V6_vunpackb : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackb">; +def int_hexagon_S2_tableidxd_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackb_128B,VD_ftype_VI,1) -// tag : V6_vunpackb_128B -def int_hexagon_V6_vunpackb_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackb_128B">; +def int_hexagon_M2_mpysu_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackuh,VD_ftype_VI,1) -// tag : V6_vunpackuh -def int_hexagon_V6_vunpackuh : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackuh">; +def int_hexagon_M2_mpyud_acc_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackuh_128B,VD_ftype_VI,1) -// tag : V6_vunpackuh_128B -def int_hexagon_V6_vunpackuh_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; +def int_hexagon_M2_mpyud_acc_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackh,VD_ftype_VI,1) -// tag : V6_vunpackh -def int_hexagon_V6_vunpackh : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vunpackh">; +def int_hexagon_M2_cmpysc_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackh_128B,VD_ftype_VI,1) -// tag : V6_vunpackh_128B -def int_hexagon_V6_vunpackh_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vunpackh_128B">; +def int_hexagon_M2_cmpysc_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackob,VD_ftype_VDVI,2) -// tag : V6_vunpackob -def int_hexagon_V6_vunpackob : -Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackob">; +def int_hexagon_M4_cmpyi_whc : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackob_128B,VD_ftype_VDVI,2) -// tag : V6_vunpackob_128B -def int_hexagon_V6_vunpackob_128B : -Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackob_128B">; +def int_hexagon_M2_mpy_sat_rnd_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackoh,VD_ftype_VDVI,2) -// tag : V6_vunpackoh -def int_hexagon_V6_vunpackoh : -Hexagon_v1024v1024v512_Intrinsic<"HEXAGON_V6_vunpackoh">; +def int_hexagon_M2_mpy_sat_rnd_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vunpackoh_128B,VD_ftype_VDVI,2) -// tag : V6_vunpackoh_128B -def int_hexagon_V6_vunpackoh_128B : -Hexagon_v2048v2048v1024_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; +def int_hexagon_S2_tableidxb_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackeb,VI_ftype_VIVI,2) -// tag : V6_vpackeb -def int_hexagon_V6_vpackeb : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeb">; +def int_hexagon_S2_shuffoh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackeb_128B,VI_ftype_VIVI,2) -// tag : V6_vpackeb_128B -def int_hexagon_V6_vpackeb_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeb_128B">; +def int_hexagon_F2_sfmax : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackeh,VI_ftype_VIVI,2) -// tag : V6_vpackeh -def int_hexagon_V6_vpackeh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackeh">; +def int_hexagon_A2_vabswsat : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackeh_128B,VI_ftype_VIVI,2) -// tag : V6_vpackeh_128B -def int_hexagon_V6_vpackeh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackeh_128B">; +def int_hexagon_S2_asr_i_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackob,VI_ftype_VIVI,2) -// tag : V6_vpackob -def int_hexagon_V6_vpackob : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackob">; +def int_hexagon_S2_asr_i_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackob_128B,VI_ftype_VIVI,2) -// tag : V6_vpackob_128B -def int_hexagon_V6_vpackob_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackob_128B">; +def int_hexagon_A4_combineri : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackoh,VI_ftype_VIVI,2) -// tag : V6_vpackoh -def int_hexagon_V6_vpackoh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackoh">; +def int_hexagon_M2_mpy_nac_sat_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackoh_128B,VI_ftype_VIVI,2) -// tag : V6_vpackoh_128B -def int_hexagon_V6_vpackoh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackoh_128B">; +def int_hexagon_M4_vpmpyh_acc : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackhub_sat,VI_ftype_VIVI,2) -// tag : V6_vpackhub_sat -def int_hexagon_V6_vpackhub_sat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhub_sat">; +def int_hexagon_M2_vcmpy_s0_sat_i : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackhub_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vpackhub_sat_128B -def int_hexagon_V6_vpackhub_sat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; +def int_hexagon_A2_notp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackhb_sat,VI_ftype_VIVI,2) -// tag : V6_vpackhb_sat -def int_hexagon_V6_vpackhb_sat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackhb_sat">; +def int_hexagon_M2_mpy_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackhb_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vpackhb_sat_128B -def int_hexagon_V6_vpackhb_sat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; +def int_hexagon_M2_mpy_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat,VI_ftype_VIVI,2) -// tag : V6_vpackwuh_sat -def int_hexagon_V6_vpackwuh_sat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; +def int_hexagon_C4_or_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackwuh_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vpackwuh_sat_128B -def int_hexagon_V6_vpackwuh_sat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; +def int_hexagon_M2_vmac2s_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackwh_sat,VI_ftype_VIVI,2) -// tag : V6_vpackwh_sat -def int_hexagon_V6_vpackwh_sat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vpackwh_sat">; +def int_hexagon_M2_vmac2s_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vpackwh_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vpackwh_sat_128B -def int_hexagon_V6_vpackwh_sat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; +def int_hexagon_S2_brevp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; -// -// BUILTIN_INFO(HEXAGON.V6_vzb,VD_ftype_VI,1) -// tag : V6_vzb -def int_hexagon_V6_vzb : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzb">; +def int_hexagon_M4_pmpyw_acc : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vzb_128B,VD_ftype_VI,1) -// tag : V6_vzb_128B -def int_hexagon_V6_vzb_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzb_128B">; +def int_hexagon_S2_cl1 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsb,VD_ftype_VI,1) -// tag : V6_vsb -def int_hexagon_V6_vsb : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsb">; +def int_hexagon_C4_cmplte : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; -// -// BUILTIN_INFO(HEXAGON.V6_vsb_128B,VD_ftype_VI,1) -// tag : V6_vsb_128B -def int_hexagon_V6_vsb_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsb_128B">; +def int_hexagon_M2_mmpyul_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vzh,VD_ftype_VI,1) -// tag : V6_vzh -def int_hexagon_V6_vzh : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vzh">; +def int_hexagon_A2_vaddws : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; -// -// BUILTIN_INFO(HEXAGON.V6_vzh_128B,VD_ftype_VI,1) -// tag : V6_vzh_128B -def int_hexagon_V6_vzh_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vzh_128B">; +def int_hexagon_A2_maxup : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; -// -// BUILTIN_INFO(HEXAGON.V6_vsh,VD_ftype_VI,1) -// tag : V6_vsh -def int_hexagon_V6_vsh : -Hexagon_v1024v512_Intrinsic<"HEXAGON_V6_vsh">; +def int_hexagon_A4_vcmphgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti">; -// -// BUILTIN_INFO(HEXAGON.V6_vsh_128B,VD_ftype_VI,1) -// tag : V6_vsh_128B -def int_hexagon_V6_vsh_128B : -Hexagon_v2048v1024_Intrinsic<"HEXAGON_V6_vsh_128B">; +def int_hexagon_S2_interleave : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus,VI_ftype_VISI,2) -// tag : V6_vdmpybus -def int_hexagon_V6_vdmpybus : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus">; +def int_hexagon_M2_vrcmpyi_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_128B,VI_ftype_VISI,2) -// tag : V6_vdmpybus_128B -def int_hexagon_V6_vdmpybus_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; +def int_hexagon_A2_abssat : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc,VI_ftype_VIVISI,3) -// tag : V6_vdmpybus_acc -def int_hexagon_V6_vdmpybus_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; +def int_hexagon_A2_vcmpwgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vdmpybus_acc_128B -def int_hexagon_V6_vdmpybus_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; +def int_hexagon_C2_cmpgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv,VD_ftype_VDSI,2) -// tag : V6_vdmpybus_dv -def int_hexagon_V6_vdmpybus_dv : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; +def int_hexagon_C2_cmpgtp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_128B,VD_ftype_VDSI,2) -// tag : V6_vdmpybus_dv_128B -def int_hexagon_V6_vdmpybus_dv_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; +def int_hexagon_A4_cmphgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc,VD_ftype_VDVDSI,3) -// tag : V6_vdmpybus_dv_acc -def int_hexagon_V6_vdmpybus_dv_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; +def int_hexagon_C2_cmpgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpybus_dv_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vdmpybus_dv_acc_128B -def int_hexagon_V6_vdmpybus_dv_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; +def int_hexagon_M2_mpyi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb,VI_ftype_VISI,2) -// tag : V6_vdmpyhb -def int_hexagon_V6_vdmpyhb : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb">; +def int_hexagon_F2_conv_df2uw_chop : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_128B,VI_ftype_VISI,2) -// tag : V6_vdmpyhb_128B -def int_hexagon_V6_vdmpyhb_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; +def int_hexagon_A4_cmpheq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhb_acc -def int_hexagon_V6_vdmpyhb_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; +def int_hexagon_M2_mpy_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhb_acc_128B -def int_hexagon_V6_vdmpyhb_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; +def int_hexagon_M2_mpy_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv,VD_ftype_VDSI,2) -// tag : V6_vdmpyhb_dv -def int_hexagon_V6_vdmpyhb_dv : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; +def int_hexagon_S2_lsr_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_128B,VD_ftype_VDSI,2) -// tag : V6_vdmpyhb_dv_128B -def int_hexagon_V6_vdmpyhb_dv_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; +def int_hexagon_S2_vrcnegh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc,VD_ftype_VDVDSI,3) -// tag : V6_vdmpyhb_dv_acc -def int_hexagon_V6_vdmpyhb_dv_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; +def int_hexagon_S2_extractup : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhb_dv_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vdmpyhb_dv_acc_128B -def int_hexagon_V6_vdmpyhb_dv_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; +def int_hexagon_S2_asr_i_p_rnd_goodsyntax : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat,VI_ftype_VIVI,2) -// tag : V6_vdmpyhvsat -def int_hexagon_V6_vdmpyhvsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; +def int_hexagon_S4_ntstbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_128B,VI_ftype_VIVI,2) -// tag : V6_vdmpyhvsat_128B -def int_hexagon_V6_vdmpyhvsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; +def int_hexagon_F2_conv_w2sf : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc,VI_ftype_VIVIVI,3) -// tag : V6_vdmpyhvsat_acc -def int_hexagon_V6_vdmpyhvsat_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; +def int_hexagon_C2_not : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhvsat_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vdmpyhvsat_acc_128B -def int_hexagon_V6_vdmpyhvsat_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; +def int_hexagon_C2_tfrpr : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsat,VI_ftype_VISI,2) -// tag : V6_vdmpyhsat -def int_hexagon_V6_vdmpyhsat : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat">; +def int_hexagon_M2_mpy_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_128B,VI_ftype_VISI,2) -// tag : V6_vdmpyhsat_128B -def int_hexagon_V6_vdmpyhsat_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; +def int_hexagon_M2_mpy_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhsat_acc -def int_hexagon_V6_vdmpyhsat_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; +def int_hexagon_A4_cmpbgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsat_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhsat_acc_128B -def int_hexagon_V6_vdmpyhsat_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; +def int_hexagon_S2_asr_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhisat,VI_ftype_VDSI,2) -// tag : V6_vdmpyhisat -def int_hexagon_V6_vdmpyhisat : -Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat">; +def int_hexagon_A4_rcmpneqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_128B,VI_ftype_VDSI,2) -// tag : V6_vdmpyhisat_128B -def int_hexagon_V6_vdmpyhisat_128B : -Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; +def int_hexagon_S2_asl_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc,VI_ftype_VIVDSI,3) -// tag : V6_vdmpyhisat_acc -def int_hexagon_V6_vdmpyhisat_acc : -Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; +def int_hexagon_M2_subacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhisat_acc_128B,VI_ftype_VIVDSI,3) -// tag : V6_vdmpyhisat_acc_128B -def int_hexagon_V6_vdmpyhisat_acc_128B : -Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; +def int_hexagon_A2_orp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat,VI_ftype_VISI,2) -// tag : V6_vdmpyhsusat -def int_hexagon_V6_vdmpyhsusat : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; +def int_hexagon_M2_mpyu_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_128B,VI_ftype_VISI,2) -// tag : V6_vdmpyhsusat_128B -def int_hexagon_V6_vdmpyhsusat_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; +def int_hexagon_M2_mpy_acc_sat_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhsusat_acc -def int_hexagon_V6_vdmpyhsusat_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; +def int_hexagon_S2_asr_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsusat_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vdmpyhsusat_acc_128B -def int_hexagon_V6_vdmpyhsusat_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; +def int_hexagon_S2_asr_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat,VI_ftype_VDSI,2) -// tag : V6_vdmpyhsuisat -def int_hexagon_V6_vdmpyhsuisat : -Hexagon_v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; +def int_hexagon_A4_cmpbgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_128B,VI_ftype_VDSI,2) -// tag : V6_vdmpyhsuisat_128B -def int_hexagon_V6_vdmpyhsuisat_128B : -Hexagon_v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; +def int_hexagon_A4_vcmpbeq_any : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc,VI_ftype_VIVDSI,3) -// tag : V6_vdmpyhsuisat_acc -def int_hexagon_V6_vdmpyhsuisat_acc : -Hexagon_v512v512v1024i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; +def int_hexagon_A4_cmpbgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti">; -// -// BUILTIN_INFO(HEXAGON.V6_vdmpyhsuisat_acc_128B,VI_ftype_VIVDSI,3) -// tag : V6_vdmpyhsuisat_acc_128B -def int_hexagon_V6_vdmpyhsuisat_acc_128B : -Hexagon_v1024v1024v2048i_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; +def int_hexagon_M2_mpyd_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyb,VD_ftype_VDSI,2) -// tag : V6_vtmpyb -def int_hexagon_V6_vtmpyb : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb">; +def int_hexagon_S2_asl_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyb_128B,VD_ftype_VDSI,2) -// tag : V6_vtmpyb_128B -def int_hexagon_V6_vtmpyb_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; +def int_hexagon_S2_lsr_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc,VD_ftype_VDVDSI,3) -// tag : V6_vtmpyb_acc -def int_hexagon_V6_vtmpyb_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; +def int_hexagon_A2_addsp : +Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyb_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vtmpyb_acc_128B -def int_hexagon_V6_vtmpyb_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; +def int_hexagon_S4_vxsubaddw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpybus,VD_ftype_VDSI,2) -// tag : V6_vtmpybus -def int_hexagon_V6_vtmpybus : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus">; +def int_hexagon_A4_vcmpheqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpybus_128B,VD_ftype_VDSI,2) -// tag : V6_vtmpybus_128B -def int_hexagon_V6_vtmpybus_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; +def int_hexagon_S4_vxsubaddh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc,VD_ftype_VDVDSI,3) -// tag : V6_vtmpybus_acc -def int_hexagon_V6_vtmpybus_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; +def int_hexagon_M4_pmpyw : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpybus_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vtmpybus_acc_128B -def int_hexagon_V6_vtmpybus_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; +def int_hexagon_S2_vsathb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyhb,VD_ftype_VDSI,2) -// tag : V6_vtmpyhb -def int_hexagon_V6_vtmpyhb : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb">; +def int_hexagon_S2_asr_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyhb_128B,VD_ftype_VDSI,2) -// tag : V6_vtmpyhb_128B -def int_hexagon_V6_vtmpyhb_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; +def int_hexagon_M2_mpyu_acc_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc,VD_ftype_VDVDSI,3) -// tag : V6_vtmpyhb_acc -def int_hexagon_V6_vtmpyhb_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; +def int_hexagon_M2_mpyu_acc_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vtmpyhb_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vtmpyhb_acc_128B -def int_hexagon_V6_vtmpyhb_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; +def int_hexagon_S2_lsl_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub,VI_ftype_VISI,2) -// tag : V6_vrmpyub -def int_hexagon_V6_vrmpyub : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub">; +def int_hexagon_A2_pxorf : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_128B,VI_ftype_VISI,2) -// tag : V6_vrmpyub_128B -def int_hexagon_V6_vrmpyub_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; +def int_hexagon_C2_cmpgei : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc,VI_ftype_VIVISI,3) -// tag : V6_vrmpyub_acc -def int_hexagon_V6_vrmpyub_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; +def int_hexagon_A2_vsubub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vrmpyub_acc_128B -def int_hexagon_V6_vrmpyub_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; +def int_hexagon_S2_asl_i_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubv,VI_ftype_VIVI,2) -// tag : V6_vrmpyubv -def int_hexagon_V6_vrmpyubv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv">; +def int_hexagon_S2_asl_i_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubv_128B,VI_ftype_VIVI,2) -// tag : V6_vrmpyubv_128B -def int_hexagon_V6_vrmpyubv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; +def int_hexagon_A4_vrminuw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc,VI_ftype_VIVIVI,3) -// tag : V6_vrmpyubv_acc -def int_hexagon_V6_vrmpyubv_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; +def int_hexagon_F2_sffma : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubv_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vrmpyubv_acc_128B -def int_hexagon_V6_vrmpyubv_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; +def int_hexagon_A2_absp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybv,VI_ftype_VIVI,2) -// tag : V6_vrmpybv -def int_hexagon_V6_vrmpybv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv">; +def int_hexagon_C2_all8 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybv_128B,VI_ftype_VIVI,2) -// tag : V6_vrmpybv_128B -def int_hexagon_V6_vrmpybv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; +def int_hexagon_A4_vrminuh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc,VI_ftype_VIVIVI,3) -// tag : V6_vrmpybv_acc -def int_hexagon_V6_vrmpybv_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; +def int_hexagon_F2_sffma_lib : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybv_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vrmpybv_acc_128B -def int_hexagon_V6_vrmpybv_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; +def int_hexagon_M4_vrmpyoh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubi,VD_ftype_VDSISI,3) -// tag : V6_vrmpyubi -def int_hexagon_V6_vrmpyubi : -Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi">; +def int_hexagon_M4_vrmpyoh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubi_128B,VD_ftype_VDSISI,3) -// tag : V6_vrmpyubi_128B -def int_hexagon_V6_vrmpyubi_128B : -Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">; +def int_hexagon_C2_bitsset : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc,VD_ftype_VDVDSISI,4) -// tag : V6_vrmpyubi_acc -def int_hexagon_V6_vrmpyubi_acc : -Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">; +def int_hexagon_M2_mpysip : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyubi_acc_128B,VD_ftype_VDVDSISI,4) -// tag : V6_vrmpyubi_acc_128B -def int_hexagon_V6_vrmpyubi_acc_128B : -Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">; +def int_hexagon_M2_mpysin : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybus,VI_ftype_VISI,2) -// tag : V6_vrmpybus -def int_hexagon_V6_vrmpybus : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus">; +def int_hexagon_A4_boundscheck : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybus_128B,VI_ftype_VISI,2) -// tag : V6_vrmpybus_128B -def int_hexagon_V6_vrmpybus_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; +def int_hexagon_M5_vrmpybuu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc,VI_ftype_VIVISI,3) -// tag : V6_vrmpybus_acc -def int_hexagon_V6_vrmpybus_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; +def int_hexagon_C4_fastcorner9 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybus_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vrmpybus_acc_128B -def int_hexagon_V6_vrmpybus_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; +def int_hexagon_M2_vrcmpys_s1rp : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusi,VD_ftype_VDSISI,3) -// tag : V6_vrmpybusi -def int_hexagon_V6_vrmpybusi : -Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi">; +def int_hexagon_A2_neg : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusi_128B,VD_ftype_VDSISI,3) -// tag : V6_vrmpybusi_128B -def int_hexagon_V6_vrmpybusi_128B : -Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">; +def int_hexagon_A2_subsat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc,VD_ftype_VDVDSISI,4) -// tag : V6_vrmpybusi_acc -def int_hexagon_V6_vrmpybusi_acc : -Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">; +def int_hexagon_S2_asl_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusi_acc_128B,VD_ftype_VDVDSISI,4) -// tag : V6_vrmpybusi_acc_128B -def int_hexagon_V6_vrmpybusi_acc_128B : -Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">; +def int_hexagon_S2_asl_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusv,VI_ftype_VIVI,2) -// tag : V6_vrmpybusv -def int_hexagon_V6_vrmpybusv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv">; +def int_hexagon_A2_vnavgh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusv_128B,VI_ftype_VIVI,2) -// tag : V6_vrmpybusv_128B -def int_hexagon_V6_vrmpybusv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; +def int_hexagon_M2_mpy_nac_sat_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc,VI_ftype_VIVIVI,3) -// tag : V6_vrmpybusv_acc -def int_hexagon_V6_vrmpybusv_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; +def int_hexagon_F2_conv_ud2df : +Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybusv_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vrmpybusv_acc_128B -def int_hexagon_V6_vrmpybusv_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; +def int_hexagon_A2_vnavgw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; -// -// BUILTIN_INFO(HEXAGON.V6_vdsaduh,VD_ftype_VDSI,2) -// tag : V6_vdsaduh -def int_hexagon_V6_vdsaduh : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh">; +def int_hexagon_S2_asl_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vdsaduh_128B,VD_ftype_VDSI,2) -// tag : V6_vdsaduh_128B -def int_hexagon_V6_vdsaduh_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; +def int_hexagon_S4_subi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc,VD_ftype_VDVDSI,3) -// tag : V6_vdsaduh_acc -def int_hexagon_V6_vdsaduh_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; +def int_hexagon_S2_vzxthw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; -// -// BUILTIN_INFO(HEXAGON.V6_vdsaduh_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vdsaduh_acc_128B -def int_hexagon_V6_vdsaduh_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; +def int_hexagon_F2_sfadd : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">; -// -// BUILTIN_INFO(HEXAGON.V6_vrsadubi,VD_ftype_VDSISI,3) -// tag : V6_vrsadubi -def int_hexagon_V6_vrsadubi : -Hexagon_v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi">; +def int_hexagon_A2_sub : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; -// -// BUILTIN_INFO(HEXAGON.V6_vrsadubi_128B,VD_ftype_VDSISI,3) -// tag : V6_vrsadubi_128B -def int_hexagon_V6_vrsadubi_128B : -Hexagon_v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_128B">; +def int_hexagon_M2_vmac2su_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc,VD_ftype_VDVDSISI,4) -// tag : V6_vrsadubi_acc -def int_hexagon_V6_vrsadubi_acc : -Hexagon_v1024v1024v1024ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc">; +def int_hexagon_M2_vmac2su_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vrsadubi_acc_128B,VD_ftype_VDVDSISI,4) -// tag : V6_vrsadubi_acc_128B -def int_hexagon_V6_vrsadubi_acc_128B : -Hexagon_v2048v2048v2048ii_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">; +def int_hexagon_M2_dpmpyss_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrw,VI_ftype_VISI,2) -// tag : V6_vasrw -def int_hexagon_V6_vasrw : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrw">; +def int_hexagon_S2_insert : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrw_128B,VI_ftype_VISI,2) -// tag : V6_vasrw_128B -def int_hexagon_V6_vasrw_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_128B">; +def int_hexagon_S2_packhl : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; +def int_hexagon_A4_vcmpwgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslw,VI_ftype_VISI,2) -// tag : V6_vaslw -def int_hexagon_V6_vaslw : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslw">; +def int_hexagon_A2_vavguwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslw_128B,VI_ftype_VISI,2) -// tag : V6_vaslw_128B -def int_hexagon_V6_vaslw_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_128B">; +def int_hexagon_S2_asl_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrw,VI_ftype_VISI,2) -// tag : V6_vlsrw -def int_hexagon_V6_vlsrw : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrw">; +def int_hexagon_A2_svsubhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrw_128B,VI_ftype_VISI,2) -// tag : V6_vlsrw_128B -def int_hexagon_V6_vlsrw_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrw_128B">; +def int_hexagon_A2_addh_l16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwv,VI_ftype_VIVI,2) -// tag : V6_vasrwv -def int_hexagon_V6_vasrwv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrwv">; +def int_hexagon_M4_and_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwv_128B,VI_ftype_VIVI,2) -// tag : V6_vasrwv_128B -def int_hexagon_V6_vasrwv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrwv_128B">; +def int_hexagon_F2_conv_d2df : +Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslwv,VI_ftype_VIVI,2) -// tag : V6_vaslwv -def int_hexagon_V6_vaslwv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslwv">; +def int_hexagon_C2_cmpgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslwv_128B,VI_ftype_VIVI,2) -// tag : V6_vaslwv_128B -def int_hexagon_V6_vaslwv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslwv_128B">; +def int_hexagon_A2_vconj : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrwv,VI_ftype_VIVI,2) -// tag : V6_vlsrwv -def int_hexagon_V6_vlsrwv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrwv">; +def int_hexagon_S2_lsr_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrwv_128B,VI_ftype_VIVI,2) -// tag : V6_vlsrwv_128B -def int_hexagon_V6_vlsrwv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; +def int_hexagon_S2_lsr_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrh,VI_ftype_VISI,2) -// tag : V6_vasrh -def int_hexagon_V6_vasrh : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vasrh">; +def int_hexagon_A2_subh_l16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrh_128B,VI_ftype_VISI,2) -// tag : V6_vasrh_128B -def int_hexagon_V6_vasrh_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_128B">; +def int_hexagon_S4_vxsubaddhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslh,VI_ftype_VISI,2) -// tag : V6_vaslh -def int_hexagon_V6_vaslh : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vaslh">; +def int_hexagon_S2_clbp : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslh_128B,VI_ftype_VISI,2) -// tag : V6_vaslh_128B -def int_hexagon_V6_vaslh_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_128B">; +def int_hexagon_S2_deinterleave : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrh,VI_ftype_VISI,2) -// tag : V6_vlsrh -def int_hexagon_V6_vlsrh : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vlsrh">; +def int_hexagon_C2_any8 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrh_128B,VI_ftype_VISI,2) -// tag : V6_vlsrh_128B -def int_hexagon_V6_vlsrh_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrh_128B">; +def int_hexagon_S2_togglebit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhv,VI_ftype_VIVI,2) -// tag : V6_vasrhv -def int_hexagon_V6_vasrhv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vasrhv">; +def int_hexagon_S2_togglebit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhv_128B,VI_ftype_VIVI,2) -// tag : V6_vasrhv_128B -def int_hexagon_V6_vasrhv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vasrhv_128B">; +def int_hexagon_F2_conv_uw2sf : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslhv,VI_ftype_VIVI,2) -// tag : V6_vaslhv -def int_hexagon_V6_vaslhv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaslhv">; +def int_hexagon_S2_vsathb_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslhv_128B,VI_ftype_VIVI,2) -// tag : V6_vaslhv_128B -def int_hexagon_V6_vaslhv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaslhv_128B">; +def int_hexagon_M2_cmacs_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrhv,VI_ftype_VIVI,2) -// tag : V6_vlsrhv -def int_hexagon_V6_vlsrhv : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vlsrhv">; +def int_hexagon_M2_cmacs_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrhv_128B,VI_ftype_VIVI,2) -// tag : V6_vlsrhv_128B -def int_hexagon_V6_vlsrhv_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; +def int_hexagon_M2_mpy_sat_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwh,VI_ftype_VIVISI,3) -// tag : V6_vasrwh -def int_hexagon_V6_vasrwh : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwh">; +def int_hexagon_M2_mpy_sat_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwh_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrwh_128B -def int_hexagon_V6_vasrwh_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwh_128B">; +def int_hexagon_M2_mmacuhs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwhsat,VI_ftype_VIVISI,3) -// tag : V6_vasrwhsat -def int_hexagon_V6_vasrwhsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhsat">; +def int_hexagon_M2_mmacuhs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwhsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrwhsat_128B -def int_hexagon_V6_vasrwhsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; +def int_hexagon_S2_clrbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasrwhrndsat -def int_hexagon_V6_vasrwhrndsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; +def int_hexagon_C4_or_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwhrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrwhrndsat_128B -def int_hexagon_V6_vasrwhrndsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; +def int_hexagon_S2_asl_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwuhsat,VI_ftype_VIVISI,3) -// tag : V6_vasrwuhsat -def int_hexagon_V6_vasrwuhsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhsat">; +def int_hexagon_S2_asl_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwuhsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrwuhsat_128B -def int_hexagon_V6_vasrwuhsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; +def int_hexagon_A4_vcmpwgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundwh,VI_ftype_VIVI,2) -// tag : V6_vroundwh -def int_hexagon_V6_vroundwh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwh">; +def int_hexagon_M4_vrmpyoh_acc_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundwh_128B,VI_ftype_VIVI,2) -// tag : V6_vroundwh_128B -def int_hexagon_V6_vroundwh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwh_128B">; +def int_hexagon_M4_vrmpyoh_acc_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundwuh,VI_ftype_VIVI,2) -// tag : V6_vroundwuh -def int_hexagon_V6_vroundwuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundwuh">; +def int_hexagon_A4_vrmaxh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundwuh_128B,VI_ftype_VIVI,2) -// tag : V6_vroundwuh_128B -def int_hexagon_V6_vroundwuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; +def int_hexagon_A2_vcmpbeq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhubsat,VI_ftype_VIVISI,3) -// tag : V6_vasrhubsat -def int_hexagon_V6_vasrhubsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubsat">; +def int_hexagon_A2_vcmphgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhubsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrhubsat_128B -def int_hexagon_V6_vasrhubsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; +def int_hexagon_A2_vnavgwcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasrhubrndsat -def int_hexagon_V6_vasrhubrndsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; +def int_hexagon_M2_vrcmacr_s0c : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhubrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrhubrndsat_128B -def int_hexagon_V6_vasrhubrndsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; +def int_hexagon_A2_vavgwcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasrhbrndsat -def int_hexagon_V6_vasrhbrndsat : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; +def int_hexagon_S2_asl_i_p_xacc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhbrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrhbrndsat_128B -def int_hexagon_V6_vasrhbrndsat_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; +def int_hexagon_A4_vrmaxw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundhb,VI_ftype_VIVI,2) -// tag : V6_vroundhb -def int_hexagon_V6_vroundhb : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhb">; +def int_hexagon_A2_vnavghr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundhb_128B,VI_ftype_VIVI,2) -// tag : V6_vroundhb_128B -def int_hexagon_V6_vroundhb_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhb_128B">; +def int_hexagon_M4_cmpyi_wh : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundhub,VI_ftype_VIVI,2) -// tag : V6_vroundhub -def int_hexagon_V6_vroundhub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vroundhub">; +def int_hexagon_A2_tfrsi : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi">; -// -// BUILTIN_INFO(HEXAGON.V6_vroundhub_128B,VI_ftype_VIVI,2) -// tag : V6_vroundhub_128B -def int_hexagon_V6_vroundhub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vroundhub_128B">; +def int_hexagon_S2_asr_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslw_acc,VI_ftype_VIVISI,3) -// tag : V6_vaslw_acc -def int_hexagon_V6_vaslw_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslw_acc">; +def int_hexagon_A2_svnavgh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslw_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vaslw_acc_128B -def int_hexagon_V6_vaslw_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; +def int_hexagon_S2_lsr_i_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrw_acc,VI_ftype_VIVISI,3) -// tag : V6_vasrw_acc -def int_hexagon_V6_vasrw_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrw_acc">; +def int_hexagon_M2_vmac2 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrw_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrw_acc_128B -def int_hexagon_V6_vasrw_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; +def int_hexagon_A4_vcmphgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddb,VI_ftype_VIVI,2) -// tag : V6_vaddb -def int_hexagon_V6_vaddb : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddb">; +def int_hexagon_A2_svavgh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddb_128B,VI_ftype_VIVI,2) -// tag : V6_vaddb_128B -def int_hexagon_V6_vaddb_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_128B">; +def int_hexagon_M4_vrmpyeh_acc_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubb,VI_ftype_VIVI,2) -// tag : V6_vsubb -def int_hexagon_V6_vsubb : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubb">; +def int_hexagon_M4_vrmpyeh_acc_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubb_128B,VI_ftype_VIVI,2) -// tag : V6_vsubb_128B -def int_hexagon_V6_vsubb_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_128B">; +def int_hexagon_S2_lsr_i_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddb_dv,VD_ftype_VDVD,2) -// tag : V6_vaddb_dv -def int_hexagon_V6_vaddb_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddb_dv">; +def int_hexagon_A2_combine_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddb_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddb_dv_128B -def int_hexagon_V6_vaddb_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; +def int_hexagon_M2_mpy_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubb_dv,VD_ftype_VDVD,2) -// tag : V6_vsubb_dv -def int_hexagon_V6_vsubb_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubb_dv">; +def int_hexagon_A2_combine_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubb_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubb_dv_128B -def int_hexagon_V6_vsubb_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; +def int_hexagon_A2_negsat : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddh,VI_ftype_VIVI,2) -// tag : V6_vaddh -def int_hexagon_V6_vaddh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddh">; +def int_hexagon_M2_mpyd_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddh_128B,VI_ftype_VIVI,2) -// tag : V6_vaddh_128B -def int_hexagon_V6_vaddh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_128B">; +def int_hexagon_M2_mpyd_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubh,VI_ftype_VIVI,2) -// tag : V6_vsubh -def int_hexagon_V6_vsubh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubh">; +def int_hexagon_A4_bitsplit : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubh_128B,VI_ftype_VIVI,2) -// tag : V6_vsubh_128B -def int_hexagon_V6_vsubh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_128B">; +def int_hexagon_A2_vabshsat : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddh_dv,VD_ftype_VDVD,2) -// tag : V6_vaddh_dv -def int_hexagon_V6_vaddh_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddh_dv">; +def int_hexagon_M2_mpyui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddh_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddh_dv_128B -def int_hexagon_V6_vaddh_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; +def int_hexagon_A2_addh_l16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubh_dv,VD_ftype_VDVD,2) -// tag : V6_vsubh_dv -def int_hexagon_V6_vsubh_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubh_dv">; +def int_hexagon_S2_lsl_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubh_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubh_dv_128B -def int_hexagon_V6_vsubh_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; +def int_hexagon_M2_mmpyul_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddw,VI_ftype_VIVI,2) -// tag : V6_vaddw -def int_hexagon_V6_vaddw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddw">; +def int_hexagon_S2_asr_i_r_rnd_goodsyntax : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddw_128B,VI_ftype_VIVI,2) -// tag : V6_vaddw_128B -def int_hexagon_V6_vaddw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_128B">; +def int_hexagon_S2_lsr_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubw,VI_ftype_VIVI,2) -// tag : V6_vsubw -def int_hexagon_V6_vsubw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubw">; +def int_hexagon_C2_cmplt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubw_128B,VI_ftype_VIVI,2) -// tag : V6_vsubw_128B -def int_hexagon_V6_vsubw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_128B">; +def int_hexagon_M2_cmacr_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddw_dv,VD_ftype_VDVD,2) -// tag : V6_vaddw_dv -def int_hexagon_V6_vaddw_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddw_dv">; +def int_hexagon_M4_or_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddw_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddw_dv_128B -def int_hexagon_V6_vaddw_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; +def int_hexagon_M4_mpyrr_addi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubw_dv,VD_ftype_VDVD,2) -// tag : V6_vsubw_dv -def int_hexagon_V6_vsubw_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubw_dv">; +def int_hexagon_S4_or_andi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubw_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubw_dv_128B -def int_hexagon_V6_vsubw_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; +def int_hexagon_M2_mpy_sat_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubsat,VI_ftype_VIVI,2) -// tag : V6_vaddubsat -def int_hexagon_V6_vaddubsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddubsat">; +def int_hexagon_M2_mpy_sat_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubsat_128B,VI_ftype_VIVI,2) -// tag : V6_vaddubsat_128B -def int_hexagon_V6_vaddubsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; +def int_hexagon_M4_mpyrr_addr : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv,VD_ftype_VDVD,2) -// tag : V6_vaddubsat_dv -def int_hexagon_V6_vaddubsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; +def int_hexagon_M2_mmachs_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddubsat_dv_128B -def int_hexagon_V6_vaddubsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; +def int_hexagon_M2_mmachs_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububsat,VI_ftype_VIVI,2) -// tag : V6_vsububsat -def int_hexagon_V6_vsububsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsububsat">; +def int_hexagon_M2_vrcmpyr_s0c : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsububsat_128B -def int_hexagon_V6_vsububsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_128B">; +def int_hexagon_M2_mpy_acc_sat_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsububsat_dv -def int_hexagon_V6_vsububsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsububsat_dv">; +def int_hexagon_M2_mpyd_acc_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsububsat_dv_128B -def int_hexagon_V6_vsububsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; +def int_hexagon_F2_sffixupn : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhsat,VI_ftype_VIVI,2) -// tag : V6_vadduhsat -def int_hexagon_V6_vadduhsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vadduhsat">; +def int_hexagon_M2_mpyd_acc_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhsat_128B,VI_ftype_VIVI,2) -// tag : V6_vadduhsat_128B -def int_hexagon_V6_vadduhsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; +def int_hexagon_M2_mpyd_acc_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv,VD_ftype_VDVD,2) -// tag : V6_vadduhsat_dv -def int_hexagon_V6_vadduhsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; +def int_hexagon_M2_mpy_rnd_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vadduhsat_dv_128B -def int_hexagon_V6_vadduhsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; +def int_hexagon_M2_mpy_rnd_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhsat,VI_ftype_VIVI,2) -// tag : V6_vsubuhsat -def int_hexagon_V6_vsubuhsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuhsat">; +def int_hexagon_A2_vadduhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubuhsat_128B -def int_hexagon_V6_vsubuhsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; +def int_hexagon_A2_vsubuhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsubuhsat_dv -def int_hexagon_V6_vsubuhsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; +def int_hexagon_A2_subh_h16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubuhsat_dv_128B -def int_hexagon_V6_vsubuhsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; +def int_hexagon_A2_subh_h16_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhsat,VI_ftype_VIVI,2) -// tag : V6_vaddhsat -def int_hexagon_V6_vaddhsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddhsat">; +def int_hexagon_A2_xorp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhsat_128B,VI_ftype_VIVI,2) -// tag : V6_vaddhsat_128B -def int_hexagon_V6_vaddhsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; +def int_hexagon_A4_tfrpcp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv,VD_ftype_VDVD,2) -// tag : V6_vaddhsat_dv -def int_hexagon_V6_vaddhsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; +def int_hexagon_A2_addh_h16_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddhsat_dv_128B -def int_hexagon_V6_vaddhsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; +def int_hexagon_A2_addh_h16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhsat,VI_ftype_VIVI,2) -// tag : V6_vsubhsat -def int_hexagon_V6_vsubhsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubhsat">; +def int_hexagon_A2_addh_h16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubhsat_128B -def int_hexagon_V6_vsubhsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; +def int_hexagon_A2_addh_h16_sat_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsubhsat_dv -def int_hexagon_V6_vsubhsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; +def int_hexagon_A2_zxtb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubhsat_dv_128B -def int_hexagon_V6_vsubhsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; +def int_hexagon_A2_zxth : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwsat,VI_ftype_VIVI,2) -// tag : V6_vaddwsat -def int_hexagon_V6_vaddwsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vaddwsat">; +def int_hexagon_A2_vnavgwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwsat_128B,VI_ftype_VIVI,2) -// tag : V6_vaddwsat_128B -def int_hexagon_V6_vaddwsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; +def int_hexagon_M4_or_xor : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv,VD_ftype_VDVD,2) -// tag : V6_vaddwsat_dv -def int_hexagon_V6_vaddwsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; +def int_hexagon_M2_mpyud_acc_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddwsat_dv_128B -def int_hexagon_V6_vaddwsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; +def int_hexagon_M2_mpyud_acc_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwsat,VI_ftype_VIVI,2) -// tag : V6_vsubwsat -def int_hexagon_V6_vsubwsat : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsubwsat">; +def int_hexagon_M5_vmacbsu : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubwsat_128B -def int_hexagon_V6_vsubwsat_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; +def int_hexagon_M2_dpmpyuu_acc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsubwsat_dv -def int_hexagon_V6_vsubwsat_dv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; +def int_hexagon_M2_mpy_rnd_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubwsat_dv_128B -def int_hexagon_V6_vsubwsat_dv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; +def int_hexagon_M2_mpy_rnd_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgub,VI_ftype_VIVI,2) -// tag : V6_vavgub -def int_hexagon_V6_vavgub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgub">; +def int_hexagon_F2_sffms_lib : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgub_128B,VI_ftype_VIVI,2) -// tag : V6_vavgub_128B -def int_hexagon_V6_vavgub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgub_128B">; +def int_hexagon_C4_cmpneqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgubrnd,VI_ftype_VIVI,2) -// tag : V6_vavgubrnd -def int_hexagon_V6_vavgubrnd : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgubrnd">; +def int_hexagon_M4_and_xor : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgubrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavgubrnd_128B -def int_hexagon_V6_vavgubrnd_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; +def int_hexagon_A2_sat : +Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguh,VI_ftype_VIVI,2) -// tag : V6_vavguh -def int_hexagon_V6_vavguh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguh">; +def int_hexagon_M2_mpyd_nac_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguh_128B,VI_ftype_VIVI,2) -// tag : V6_vavguh_128B -def int_hexagon_V6_vavguh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguh_128B">; +def int_hexagon_M2_mpyd_nac_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguhrnd,VI_ftype_VIVI,2) -// tag : V6_vavguhrnd -def int_hexagon_V6_vavguhrnd : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavguhrnd">; +def int_hexagon_A2_addsat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguhrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavguhrnd_128B -def int_hexagon_V6_vavguhrnd_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; +def int_hexagon_A2_svavghs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgh,VI_ftype_VIVI,2) -// tag : V6_vavgh -def int_hexagon_V6_vavgh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgh">; +def int_hexagon_A2_vrsadub_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgh_128B,VI_ftype_VIVI,2) -// tag : V6_vavgh_128B -def int_hexagon_V6_vavgh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgh_128B">; +def int_hexagon_C2_bitsclri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri">; -// -// BUILTIN_INFO(HEXAGON.V6_vavghrnd,VI_ftype_VIVI,2) -// tag : V6_vavghrnd -def int_hexagon_V6_vavghrnd : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavghrnd">; +def int_hexagon_A2_subh_h16_sat_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; -// -// BUILTIN_INFO(HEXAGON.V6_vavghrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavghrnd_128B -def int_hexagon_V6_vavghrnd_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; +def int_hexagon_A2_subh_h16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgh,VI_ftype_VIVI,2) -// tag : V6_vnavgh -def int_hexagon_V6_vnavgh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgh">; +def int_hexagon_M2_mmaculs_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgh_128B,VI_ftype_VIVI,2) -// tag : V6_vnavgh_128B -def int_hexagon_V6_vnavgh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgh_128B">; +def int_hexagon_M2_mmaculs_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgw,VI_ftype_VIVI,2) -// tag : V6_vavgw -def int_hexagon_V6_vavgw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgw">; +def int_hexagon_M2_vradduh : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgw_128B,VI_ftype_VIVI,2) -// tag : V6_vavgw_128B -def int_hexagon_V6_vavgw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgw_128B">; +def int_hexagon_A4_addp_c : +Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgwrnd,VI_ftype_VIVI,2) -// tag : V6_vavgwrnd -def int_hexagon_V6_vavgwrnd : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vavgwrnd">; +def int_hexagon_C2_xor : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgwrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavgwrnd_128B -def int_hexagon_V6_vavgwrnd_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; +def int_hexagon_S2_lsl_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgw,VI_ftype_VIVI,2) -// tag : V6_vnavgw -def int_hexagon_V6_vnavgw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgw">; +def int_hexagon_M2_mmpyh_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgw_128B,VI_ftype_VIVI,2) -// tag : V6_vnavgw_128B -def int_hexagon_V6_vnavgw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgw_128B">; +def int_hexagon_M2_mmpyh_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffub,VI_ftype_VIVI,2) -// tag : V6_vabsdiffub -def int_hexagon_V6_vabsdiffub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffub">; +def int_hexagon_F2_conv_df2ud_chop : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffub_128B,VI_ftype_VIVI,2) -// tag : V6_vabsdiffub_128B -def int_hexagon_V6_vabsdiffub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; +def int_hexagon_C4_or_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffuh,VI_ftype_VIVI,2) -// tag : V6_vabsdiffuh -def int_hexagon_V6_vabsdiffuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffuh">; +def int_hexagon_S4_vxaddsubhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffuh_128B,VI_ftype_VIVI,2) -// tag : V6_vabsdiffuh_128B -def int_hexagon_V6_vabsdiffuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; +def int_hexagon_S2_vsathub : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffh,VI_ftype_VIVI,2) -// tag : V6_vabsdiffh -def int_hexagon_V6_vabsdiffh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffh">; +def int_hexagon_F2_conv_df2sf : +Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffh_128B,VI_ftype_VIVI,2) -// tag : V6_vabsdiffh_128B -def int_hexagon_V6_vabsdiffh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; +def int_hexagon_M2_hmmpyh_rs1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffw,VI_ftype_VIVI,2) -// tag : V6_vabsdiffw -def int_hexagon_V6_vabsdiffw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vabsdiffw">; +def int_hexagon_M2_hmmpyh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsdiffw_128B,VI_ftype_VIVI,2) -// tag : V6_vabsdiffw_128B -def int_hexagon_V6_vabsdiffw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; +def int_hexagon_A2_vavgwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgub,VI_ftype_VIVI,2) -// tag : V6_vnavgub -def int_hexagon_V6_vnavgub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgub">; +def int_hexagon_S2_tableidxh_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgub_128B,VI_ftype_VIVI,2) -// tag : V6_vnavgub_128B -def int_hexagon_V6_vnavgub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgub_128B">; +def int_hexagon_A2_sxth : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubh,VD_ftype_VIVI,2) -// tag : V6_vaddubh -def int_hexagon_V6_vaddubh : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh">; +def int_hexagon_A2_sxtb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubh_128B,VD_ftype_VIVI,2) -// tag : V6_vaddubh_128B -def int_hexagon_V6_vaddubh_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_128B">; +def int_hexagon_C4_or_orn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububh,VD_ftype_VIVI,2) -// tag : V6_vsububh -def int_hexagon_V6_vsububh : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsububh">; +def int_hexagon_M2_vrcmaci_s0c : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; -// -// BUILTIN_INFO(HEXAGON.V6_vsububh_128B,VD_ftype_VIVI,2) -// tag : V6_vsububh_128B -def int_hexagon_V6_vsububh_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsububh_128B">; +def int_hexagon_A2_sxtw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhw,VD_ftype_VIVI,2) -// tag : V6_vaddhw -def int_hexagon_V6_vaddhw : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw">; +def int_hexagon_M2_vabsdiffh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhw_128B,VD_ftype_VIVI,2) -// tag : V6_vaddhw_128B -def int_hexagon_V6_vaddhw_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_128B">; +def int_hexagon_M2_mpy_acc_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhw,VD_ftype_VIVI,2) -// tag : V6_vsubhw -def int_hexagon_V6_vsubhw : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubhw">; +def int_hexagon_M2_mpy_acc_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhw_128B,VD_ftype_VIVI,2) -// tag : V6_vsubhw_128B -def int_hexagon_V6_vsubhw_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubhw_128B">; +def int_hexagon_M2_hmmpyl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhw,VD_ftype_VIVI,2) -// tag : V6_vadduhw -def int_hexagon_V6_vadduhw : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw">; +def int_hexagon_S2_cl1p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhw_128B,VD_ftype_VIVI,2) -// tag : V6_vadduhw_128B -def int_hexagon_V6_vadduhw_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_128B">; +def int_hexagon_M2_vabsdiffw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhw,VD_ftype_VIVI,2) -// tag : V6_vsubuhw -def int_hexagon_V6_vsubuhw : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vsubuhw">; +def int_hexagon_A4_andnp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuhw_128B,VD_ftype_VIVI,2) -// tag : V6_vsubuhw_128B -def int_hexagon_V6_vsubuhw_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; +def int_hexagon_C2_vmux : +Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; -// -// BUILTIN_INFO(HEXAGON.V6_vd0,VI_ftype_,0) -// tag : V6_vd0 -def int_hexagon_V6_vd0 : -Hexagon_v512_Intrinsic<"HEXAGON_V6_vd0">; +def int_hexagon_S2_parityp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; -// -// BUILTIN_INFO(HEXAGON.V6_vd0_128B,VI_ftype_,0) -// tag : V6_vd0_128B -def int_hexagon_V6_vd0_128B : -Hexagon_v1024_Intrinsic<"HEXAGON_V6_vd0_128B">; +def int_hexagon_S2_lsr_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbq,VI_ftype_QVVIVI,3) -// tag : V6_vaddbq -def int_hexagon_V6_vaddbq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbq">; +def int_hexagon_S2_asr_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddbq_128B -def int_hexagon_V6_vaddbq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbq_128B">; +def int_hexagon_M2_mpyu_nac_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; +def int_hexagon_M2_mpyu_nac_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbq,VI_ftype_QVVIVI,3) -// tag : V6_vsubbq -def int_hexagon_V6_vsubbq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbq">; +def int_hexagon_F2_sfcmpeq : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubbq_128B -def int_hexagon_V6_vsubbq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbq_128B">; +def int_hexagon_A2_vaddb_map : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbnq,VI_ftype_QVVIVI,3) -// tag : V6_vaddbnq -def int_hexagon_V6_vaddbnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddbnq">; +def int_hexagon_S2_lsr_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddbnq_128B -def int_hexagon_V6_vaddbnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; +def int_hexagon_A2_vcmpheq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbnq,VI_ftype_QVVIVI,3) -// tag : V6_vsubbnq -def int_hexagon_V6_vsubbnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubbnq">; +def int_hexagon_S2_clbnorm : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubbnq_128B -def int_hexagon_V6_vsubbnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; +def int_hexagon_M2_cnacsc_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhq,VI_ftype_QVVIVI,3) -// tag : V6_vaddhq -def int_hexagon_V6_vaddhq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhq">; +def int_hexagon_M2_cnacsc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddhq_128B -def int_hexagon_V6_vaddhq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhq_128B">; +def int_hexagon_S4_subaddi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhq,VI_ftype_QVVIVI,3) -// tag : V6_vsubhq -def int_hexagon_V6_vsubhq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhq">; +def int_hexagon_M2_mpyud_nac_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubhq_128B -def int_hexagon_V6_vsubhq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhq_128B">; +def int_hexagon_M2_mpyud_nac_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhnq,VI_ftype_QVVIVI,3) -// tag : V6_vaddhnq -def int_hexagon_V6_vaddhnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddhnq">; +def int_hexagon_S5_vasrhrnd_goodsyntax : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddhnq_128B -def int_hexagon_V6_vaddhnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; +def int_hexagon_S2_tstbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhnq,VI_ftype_QVVIVI,3) -// tag : V6_vsubhnq -def int_hexagon_V6_vsubhnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubhnq">; +def int_hexagon_S4_vrcrotate : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubhnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubhnq_128B -def int_hexagon_V6_vsubhnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; +def int_hexagon_M2_mmachs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwq,VI_ftype_QVVIVI,3) -// tag : V6_vaddwq -def int_hexagon_V6_vaddwq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwq">; +def int_hexagon_M2_mmachs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddwq_128B -def int_hexagon_V6_vaddwq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwq_128B">; +def int_hexagon_S2_tstbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwq,VI_ftype_QVVIVI,3) -// tag : V6_vsubwq -def int_hexagon_V6_vsubwq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwq">; +def int_hexagon_M2_mpy_up_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubwq_128B -def int_hexagon_V6_vsubwq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwq_128B">; +def int_hexagon_S2_extractu_rp : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwnq,VI_ftype_QVVIVI,3) -// tag : V6_vaddwnq -def int_hexagon_V6_vaddwnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vaddwnq">; +def int_hexagon_M2_mmpyuh_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddwnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vaddwnq_128B -def int_hexagon_V6_vaddwnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; +def int_hexagon_S2_lsr_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwnq,VI_ftype_QVVIVI,3) -// tag : V6_vsubwnq -def int_hexagon_V6_vsubwnq : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vsubwnq">; +def int_hexagon_M2_mpy_rnd_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubwnq_128B,VI_ftype_QVVIVI,3) -// tag : V6_vsubwnq_128B -def int_hexagon_V6_vsubwnq_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; +def int_hexagon_M2_mpy_rnd_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsh,VI_ftype_VI,1) -// tag : V6_vabsh -def int_hexagon_V6_vabsh : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh">; +def int_hexagon_M4_or_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsh_128B,VI_ftype_VI,1) -// tag : V6_vabsh_128B -def int_hexagon_V6_vabsh_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_128B">; +def int_hexagon_M2_mpyu_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsh_sat,VI_ftype_VI,1) -// tag : V6_vabsh_sat -def int_hexagon_V6_vabsh_sat : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsh_sat">; +def int_hexagon_M2_mpyu_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsh_sat_128B,VI_ftype_VI,1) -// tag : V6_vabsh_sat_128B -def int_hexagon_V6_vabsh_sat_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; +def int_hexagon_S2_asl_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsw,VI_ftype_VI,1) -// tag : V6_vabsw -def int_hexagon_V6_vabsw : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw">; +def int_hexagon_M2_mpyu_nac_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsw_128B,VI_ftype_VI,1) -// tag : V6_vabsw_128B -def int_hexagon_V6_vabsw_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_128B">; +def int_hexagon_M2_mpyu_nac_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsw_sat,VI_ftype_VI,1) -// tag : V6_vabsw_sat -def int_hexagon_V6_vabsw_sat : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vabsw_sat">; +def int_hexagon_M2_mpy_sat_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsw_sat_128B,VI_ftype_VI,1) -// tag : V6_vabsw_sat_128B -def int_hexagon_V6_vabsw_sat_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; +def int_hexagon_M2_mpy_sat_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybv,VD_ftype_VIVI,2) -// tag : V6_vmpybv -def int_hexagon_V6_vmpybv : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv">; +def int_hexagon_F2_conv_w2df : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybv_128B,VD_ftype_VIVI,2) -// tag : V6_vmpybv_128B -def int_hexagon_V6_vmpybv_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_128B">; +def int_hexagon_A2_subh_l16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybv_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpybv_acc -def int_hexagon_V6_vmpybv_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybv_acc">; +def int_hexagon_C2_cmpeqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybv_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpybv_acc_128B -def int_hexagon_V6_vmpybv_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; +def int_hexagon_S2_asl_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyubv,VD_ftype_VIVI,2) -// tag : V6_vmpyubv -def int_hexagon_V6_vmpyubv : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv">; +def int_hexagon_S2_vcnegh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyubv_128B,VD_ftype_VIVI,2) -// tag : V6_vmpyubv_128B -def int_hexagon_V6_vmpyubv_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; +def int_hexagon_A4_vcmpweqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpyubv_acc -def int_hexagon_V6_vmpyubv_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; +def int_hexagon_M2_vdmpyrs_s0 : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyubv_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpyubv_acc_128B -def int_hexagon_V6_vmpyubv_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; +def int_hexagon_M2_vdmpyrs_s1 : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybusv,VD_ftype_VIVI,2) -// tag : V6_vmpybusv -def int_hexagon_V6_vmpybusv : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv">; +def int_hexagon_M4_xor_xacc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybusv_128B,VD_ftype_VIVI,2) -// tag : V6_vmpybusv_128B -def int_hexagon_V6_vmpybusv_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; +def int_hexagon_M2_vdmpys_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpybusv_acc -def int_hexagon_V6_vmpybusv_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; +def int_hexagon_M2_vdmpys_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybusv_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpybusv_acc_128B -def int_hexagon_V6_vmpybusv_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; +def int_hexagon_A2_vavgubr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabusv,VD_ftype_VDVD,2) -// tag : V6_vmpabusv -def int_hexagon_V6_vmpabusv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabusv">; +def int_hexagon_M2_mpyu_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabusv_128B,VD_ftype_VDVD,2) -// tag : V6_vmpabusv_128B -def int_hexagon_V6_vmpabusv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; +def int_hexagon_M2_mpyu_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuuv,VD_ftype_VDVD,2) -// tag : V6_vmpabuuv -def int_hexagon_V6_vmpabuuv : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpabuuv">; +def int_hexagon_S2_asl_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuuv_128B,VD_ftype_VDVD,2) -// tag : V6_vmpabuuv_128B -def int_hexagon_V6_vmpabuuv_128B : -Hexagon_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; +def int_hexagon_S2_cl0p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhv,VD_ftype_VIVI,2) -// tag : V6_vmpyhv -def int_hexagon_V6_vmpyhv : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv">; +def int_hexagon_S2_valignib : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhv_128B,VD_ftype_VIVI,2) -// tag : V6_vmpyhv_128B -def int_hexagon_V6_vmpyhv_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; +def int_hexagon_F2_sffixupd : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpyhv_acc -def int_hexagon_V6_vmpyhv_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; +def int_hexagon_M2_mpy_sat_rnd_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhv_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpyhv_acc_128B -def int_hexagon_V6_vmpyhv_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; +def int_hexagon_M2_mpy_sat_rnd_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhv,VD_ftype_VIVI,2) -// tag : V6_vmpyuhv -def int_hexagon_V6_vmpyuhv : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv">; +def int_hexagon_M2_cmacsc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhv_128B,VD_ftype_VIVI,2) -// tag : V6_vmpyuhv_128B -def int_hexagon_V6_vmpyuhv_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; +def int_hexagon_M2_cmacsc_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpyuhv_acc -def int_hexagon_V6_vmpyuhv_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; +def int_hexagon_S2_ct1 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhv_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpyuhv_acc_128B -def int_hexagon_V6_vmpyuhv_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; +def int_hexagon_S2_ct0 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs,VI_ftype_VIVI,2) -// tag : V6_vmpyhvsrs -def int_hexagon_V6_vmpyhvsrs : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; +def int_hexagon_M2_dpmpyuu_nac_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhvsrs_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyhvsrs_128B -def int_hexagon_V6_vmpyhvsrs_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; +def int_hexagon_M2_mmpyul_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhus,VD_ftype_VIVI,2) -// tag : V6_vmpyhus -def int_hexagon_V6_vmpyhus : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus">; +def int_hexagon_S4_ntstbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhus_128B,VD_ftype_VIVI,2) -// tag : V6_vmpyhus_128B -def int_hexagon_V6_vmpyhus_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; +def int_hexagon_F2_sffixupr : +Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpyhus_acc -def int_hexagon_V6_vmpyhus_acc : -Hexagon_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; +def int_hexagon_S2_asr_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhus_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpyhus_acc_128B -def int_hexagon_V6_vmpyhus_acc_128B : -Hexagon_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; +def int_hexagon_M2_mpyud_acc_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyih,VI_ftype_VIVI,2) -// tag : V6_vmpyih -def int_hexagon_V6_vmpyih : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih">; +def int_hexagon_M2_mpyud_acc_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyih_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyih_128B -def int_hexagon_V6_vmpyih_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_128B">; +def int_hexagon_A2_vcmphgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyih_acc,VI_ftype_VIVIVI,3) -// tag : V6_vmpyih_acc -def int_hexagon_V6_vmpyih_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyih_acc">; +def int_hexagon_C2_andn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyih_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vmpyih_acc_128B -def int_hexagon_V6_vmpyih_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; +def int_hexagon_M2_vmpy2s_s0pack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyewuh,VI_ftype_VIVI,2) -// tag : V6_vmpyewuh -def int_hexagon_V6_vmpyewuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh">; +def int_hexagon_S4_addaddi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyewuh_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyewuh_128B -def int_hexagon_V6_vmpyewuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; +def int_hexagon_M2_mpyd_acc_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh,VI_ftype_VIVI,2) -// tag : V6_vmpyowh -def int_hexagon_V6_vmpyowh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh">; +def int_hexagon_M2_mpy_acc_sat_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyowh_128B -def int_hexagon_V6_vmpyowh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; +def int_hexagon_A4_rcmpeqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd,VI_ftype_VIVI,2) -// tag : V6_vmpyowh_rnd -def int_hexagon_V6_vmpyowh_rnd : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; +def int_hexagon_M4_xor_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyowh_rnd_128B -def int_hexagon_V6_vmpyowh_rnd_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; +def int_hexagon_S2_asl_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc,VI_ftype_VIVIVI,3) -// tag : V6_vmpyowh_sacc -def int_hexagon_V6_vmpyowh_sacc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; +def int_hexagon_M2_mmpyuh_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_sacc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vmpyowh_sacc_128B -def int_hexagon_V6_vmpyowh_sacc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; +def int_hexagon_S2_asr_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc,VI_ftype_VIVIVI,3) -// tag : V6_vmpyowh_rnd_sacc -def int_hexagon_V6_vmpyowh_rnd_sacc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; +def int_hexagon_A4_round_ri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_rnd_sacc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vmpyowh_rnd_sacc_128B -def int_hexagon_V6_vmpyowh_rnd_sacc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; +def int_hexagon_A2_max : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyieoh,VI_ftype_VIVI,2) -// tag : V6_vmpyieoh -def int_hexagon_V6_vmpyieoh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyieoh">; +def int_hexagon_A4_round_rr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyieoh_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyieoh_128B -def int_hexagon_V6_vmpyieoh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; +def int_hexagon_A4_combineii : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewuh,VI_ftype_VIVI,2) -// tag : V6_vmpyiewuh -def int_hexagon_V6_vmpyiewuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh">; +def int_hexagon_A4_combineir : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyiewuh_128B -def int_hexagon_V6_vmpyiewuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; +def int_hexagon_C4_and_orn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiowh,VI_ftype_VIVI,2) -// tag : V6_vmpyiowh -def int_hexagon_V6_vmpyiowh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiowh">; +def int_hexagon_M5_vmacbuu : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiowh_128B,VI_ftype_VIVI,2) -// tag : V6_vmpyiowh_128B -def int_hexagon_V6_vmpyiowh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; +def int_hexagon_A4_rcmpeq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc,VI_ftype_VIVIVI,3) -// tag : V6_vmpyiewh_acc -def int_hexagon_V6_vmpyiewh_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; +def int_hexagon_M4_cmpyr_whc : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewh_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vmpyiewh_acc_128B -def int_hexagon_V6_vmpyiewh_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; +def int_hexagon_S2_lsr_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc,VI_ftype_VIVIVI,3) -// tag : V6_vmpyiewuh_acc -def int_hexagon_V6_vmpyiewuh_acc : -Hexagon_v512v512v512v512_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; +def int_hexagon_S2_vzxtbh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiewuh_acc_128B,VI_ftype_VIVIVI,3) -// tag : V6_vmpyiewuh_acc_128B -def int_hexagon_V6_vmpyiewuh_acc_128B : -Hexagon_v1024v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; +def int_hexagon_M2_mmacuhs_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyub,VD_ftype_VISI,2) -// tag : V6_vmpyub -def int_hexagon_V6_vmpyub : -Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub">; +def int_hexagon_S2_asr_r_r_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyub_128B,VD_ftype_VISI,2) -// tag : V6_vmpyub_128B -def int_hexagon_V6_vmpyub_128B : -Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_128B">; +def int_hexagon_A2_combinew : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyub_acc,VD_ftype_VDVISI,3) -// tag : V6_vmpyub_acc -def int_hexagon_V6_vmpyub_acc : -Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyub_acc">; +def int_hexagon_M2_mpy_acc_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyub_acc_128B,VD_ftype_VDVISI,3) -// tag : V6_vmpyub_acc_128B -def int_hexagon_V6_vmpyub_acc_128B : -Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; +def int_hexagon_M2_mpy_acc_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybus,VD_ftype_VISI,2) -// tag : V6_vmpybus -def int_hexagon_V6_vmpybus : -Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus">; +def int_hexagon_M2_cmpyi_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybus_128B,VD_ftype_VISI,2) -// tag : V6_vmpybus_128B -def int_hexagon_V6_vmpybus_128B : -Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_128B">; +def int_hexagon_S2_asl_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybus_acc,VD_ftype_VDVISI,3) -// tag : V6_vmpybus_acc -def int_hexagon_V6_vmpybus_acc : -Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpybus_acc">; +def int_hexagon_S4_ori_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpybus_acc_128B,VD_ftype_VDVISI,3) -// tag : V6_vmpybus_acc_128B -def int_hexagon_V6_vmpybus_acc_128B : -Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; +def int_hexagon_C4_nbitsset : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabus,VD_ftype_VDSI,2) -// tag : V6_vmpabus -def int_hexagon_V6_vmpabus : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus">; +def int_hexagon_M2_mpyu_acc_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabus_128B,VD_ftype_VDSI,2) -// tag : V6_vmpabus_128B -def int_hexagon_V6_vmpabus_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_128B">; +def int_hexagon_M2_mpyu_acc_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabus_acc,VD_ftype_VDVDSI,3) -// tag : V6_vmpabus_acc -def int_hexagon_V6_vmpabus_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabus_acc">; +def int_hexagon_M2_mpyu_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabus_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vmpabus_acc_128B -def int_hexagon_V6_vmpabus_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; +def int_hexagon_M2_mpyu_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahb,VD_ftype_VDSI,2) -// tag : V6_vmpahb -def int_hexagon_V6_vmpahb : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb">; +def int_hexagon_A2_addh_l16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahb_128B,VD_ftype_VDSI,2) -// tag : V6_vmpahb_128B -def int_hexagon_V6_vmpahb_128B : -Hexagon_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_128B">; +def int_hexagon_S2_lsr_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahb_acc,VD_ftype_VDVDSI,3) -// tag : V6_vmpahb_acc -def int_hexagon_V6_vmpahb_acc : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpahb_acc">; +def int_hexagon_A4_modwrapu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahb_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vmpahb_acc_128B -def int_hexagon_V6_vmpahb_acc_128B : -Hexagon_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; +def int_hexagon_A4_rcmpneq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyh,VD_ftype_VISI,2) -// tag : V6_vmpyh -def int_hexagon_V6_vmpyh : -Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh">; +def int_hexagon_M2_mpyd_acc_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyh_128B,VD_ftype_VISI,2) -// tag : V6_vmpyh_128B -def int_hexagon_V6_vmpyh_128B : -Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_128B">; +def int_hexagon_M2_mpyd_acc_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc,VD_ftype_VDVISI,3) -// tag : V6_vmpyhsat_acc -def int_hexagon_V6_vmpyhsat_acc : -Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; +def int_hexagon_F2_sfimm_p : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhsat_acc_128B,VD_ftype_VDVISI,3) -// tag : V6_vmpyhsat_acc_128B -def int_hexagon_V6_vmpyhsat_acc_128B : -Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; +def int_hexagon_F2_sfimm_n : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhss,VI_ftype_VISI,2) -// tag : V6_vmpyhss -def int_hexagon_V6_vmpyhss : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhss">; +def int_hexagon_M4_cmpyr_wh : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhss_128B,VI_ftype_VISI,2) -// tag : V6_vmpyhss_128B -def int_hexagon_V6_vmpyhss_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; +def int_hexagon_S2_lsl_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhsrs,VI_ftype_VISI,2) -// tag : V6_vmpyhsrs -def int_hexagon_V6_vmpyhsrs : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyhsrs">; +def int_hexagon_A2_vavgub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyhsrs_128B,VI_ftype_VISI,2) -// tag : V6_vmpyhsrs_128B -def int_hexagon_V6_vmpyhsrs_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; +def int_hexagon_F2_conv_d2sf : +Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuh,VD_ftype_VISI,2) -// tag : V6_vmpyuh -def int_hexagon_V6_vmpyuh : -Hexagon_v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh">; +def int_hexagon_A2_vavguh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuh_128B,VD_ftype_VISI,2) -// tag : V6_vmpyuh_128B -def int_hexagon_V6_vmpyuh_128B : -Hexagon_v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; +def int_hexagon_A4_cmpbeqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc,VD_ftype_VDVISI,3) -// tag : V6_vmpyuh_acc -def int_hexagon_V6_vmpyuh_acc : -Hexagon_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; +def int_hexagon_F2_sfcmpuo : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuh_acc_128B,VD_ftype_VDVISI,3) -// tag : V6_vmpyuh_acc_128B -def int_hexagon_V6_vmpyuh_acc_128B : -Hexagon_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; +def int_hexagon_A2_vavguw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyihb,VI_ftype_VISI,2) -// tag : V6_vmpyihb -def int_hexagon_V6_vmpyihb : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb">; +def int_hexagon_S2_asr_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyihb_128B,VI_ftype_VISI,2) -// tag : V6_vmpyihb_128B -def int_hexagon_V6_vmpyihb_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; +def int_hexagon_S2_vsatwh_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc,VI_ftype_VIVISI,3) -// tag : V6_vmpyihb_acc -def int_hexagon_V6_vmpyihb_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; +def int_hexagon_M2_mpyd_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyihb_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vmpyihb_acc_128B -def int_hexagon_V6_vmpyihb_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; +def int_hexagon_M2_mpyd_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwb,VI_ftype_VISI,2) -// tag : V6_vmpyiwb -def int_hexagon_V6_vmpyiwb : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb">; +def int_hexagon_S2_lsl_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwb_128B,VI_ftype_VISI,2) -// tag : V6_vmpyiwb_128B -def int_hexagon_V6_vmpyiwb_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; +def int_hexagon_A2_minu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwb_acc -def int_hexagon_V6_vmpyiwb_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; +def int_hexagon_M2_mpy_sat_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwb_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwb_acc_128B -def int_hexagon_V6_vmpyiwb_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; +def int_hexagon_M4_or_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwh,VI_ftype_VISI,2) -// tag : V6_vmpyiwh -def int_hexagon_V6_vmpyiwh : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh">; +def int_hexagon_A2_minp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwh_128B,VI_ftype_VISI,2) -// tag : V6_vmpyiwh_128B -def int_hexagon_V6_vmpyiwh_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; +def int_hexagon_S4_or_andix : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwh_acc -def int_hexagon_V6_vmpyiwh_acc : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; +def int_hexagon_M2_mpy_rnd_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwh_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwh_acc_128B -def int_hexagon_V6_vmpyiwh_acc_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; +def int_hexagon_M2_mpy_rnd_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vand,VI_ftype_VIVI,2) -// tag : V6_vand -def int_hexagon_V6_vand : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vand">; +def int_hexagon_M2_mmpyuh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vand_128B,VI_ftype_VIVI,2) -// tag : V6_vand_128B -def int_hexagon_V6_vand_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vand_128B">; +def int_hexagon_M2_mmpyuh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vor,VI_ftype_VIVI,2) -// tag : V6_vor -def int_hexagon_V6_vor : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vor">; +def int_hexagon_M2_mpy_acc_sat_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vor_128B,VI_ftype_VIVI,2) -// tag : V6_vor_128B -def int_hexagon_V6_vor_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vor_128B">; +def int_hexagon_F2_sfcmpge : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">; -// -// BUILTIN_INFO(HEXAGON.V6_vxor,VI_ftype_VIVI,2) -// tag : V6_vxor -def int_hexagon_V6_vxor : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vxor">; +def int_hexagon_F2_sfmin : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">; -// -// BUILTIN_INFO(HEXAGON.V6_vxor_128B,VI_ftype_VIVI,2) -// tag : V6_vxor_128B -def int_hexagon_V6_vxor_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vxor_128B">; +def int_hexagon_F2_sfcmpgt : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">; -// -// BUILTIN_INFO(HEXAGON.V6_vnot,VI_ftype_VI,1) -// tag : V6_vnot -def int_hexagon_V6_vnot : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnot">; +def int_hexagon_M4_vpmpyh : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; -// -// BUILTIN_INFO(HEXAGON.V6_vnot_128B,VI_ftype_VI,1) -// tag : V6_vnot_128B -def int_hexagon_V6_vnot_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnot_128B">; +def int_hexagon_M2_mmacuhs_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; -// -// BUILTIN_INFO(HEXAGON.V6_vandqrt,VI_ftype_QVSI,2) -// tag : V6_vandqrt -def int_hexagon_V6_vandqrt : -Hexagon_v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt">; +def int_hexagon_M2_mpyd_rnd_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vandqrt_128B,VI_ftype_QVSI,2) -// tag : V6_vandqrt_128B -def int_hexagon_V6_vandqrt_128B : -Hexagon_v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_128B">; +def int_hexagon_M2_mpyd_rnd_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vandqrt_acc,VI_ftype_VIQVSI,3) -// tag : V6_vandqrt_acc -def int_hexagon_V6_vandqrt_acc : -Hexagon_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandqrt_acc">; +def int_hexagon_A2_roundsat : +Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vandqrt_acc_128B,VI_ftype_VIQVSI,3) -// tag : V6_vandqrt_acc_128B -def int_hexagon_V6_vandqrt_acc_128B : -Hexagon_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; +def int_hexagon_S2_ct1p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvrt,QV_ftype_VISI,2) -// tag : V6_vandvrt -def int_hexagon_V6_vandvrt : -Hexagon_v64iv512i_Intrinsic<"HEXAGON_V6_vandvrt">; +def int_hexagon_S4_extract_rp : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvrt_128B,QV_ftype_VISI,2) -// tag : V6_vandvrt_128B -def int_hexagon_V6_vandvrt_128B : -Hexagon_v128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_128B">; +def int_hexagon_S2_lsl_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvrt_acc,QV_ftype_QVVISI,3) -// tag : V6_vandvrt_acc -def int_hexagon_V6_vandvrt_acc : -Hexagon_v64iv64iv512i_Intrinsic<"HEXAGON_V6_vandvrt_acc">; +def int_hexagon_C4_cmplteui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvrt_acc_128B,QV_ftype_QVVISI,3) -// tag : V6_vandvrt_acc_128B -def int_hexagon_V6_vandvrt_acc_128B : -Hexagon_v128iv128iv1024i_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; +def int_hexagon_S4_addi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw,QV_ftype_VIVI,2) -// tag : V6_vgtw -def int_hexagon_V6_vgtw : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtw">; +def int_hexagon_A4_tfrcpp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_128B,QV_ftype_VIVI,2) -// tag : V6_vgtw_128B -def int_hexagon_V6_vgtw_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_128B">; +def int_hexagon_S2_asr_i_svw_trun : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_and,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_and -def int_hexagon_V6_vgtw_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_and">; +def int_hexagon_A4_cmphgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_and_128B -def int_hexagon_V6_vgtw_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; +def int_hexagon_A4_vrminh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_or,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_or -def int_hexagon_V6_vgtw_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_or">; +def int_hexagon_A4_vrminw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_or_128B -def int_hexagon_V6_vgtw_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; +def int_hexagon_A4_cmphgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_xor -def int_hexagon_V6_vgtw_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtw_xor">; +def int_hexagon_S2_insertp_rp : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtw_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtw_xor_128B -def int_hexagon_V6_vgtw_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; +def int_hexagon_A2_vnavghcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw,QV_ftype_VIVI,2) -// tag : V6_veqw -def int_hexagon_V6_veqw : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqw">; +def int_hexagon_S4_subi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_128B,QV_ftype_VIVI,2) -// tag : V6_veqw_128B -def int_hexagon_V6_veqw_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_128B">; +def int_hexagon_S2_lsl_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_and,QV_ftype_QVVIVI,3) -// tag : V6_veqw_and -def int_hexagon_V6_veqw_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_and">; +def int_hexagon_M2_mpy_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqw_and_128B -def int_hexagon_V6_veqw_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_and_128B">; +def int_hexagon_A2_vsubws : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_or,QV_ftype_QVVIVI,3) -// tag : V6_veqw_or -def int_hexagon_V6_veqw_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_or">; +def int_hexagon_A2_sath : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqw_or_128B -def int_hexagon_V6_veqw_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_or_128B">; +def int_hexagon_S2_asl_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_xor,QV_ftype_QVVIVI,3) -// tag : V6_veqw_xor -def int_hexagon_V6_veqw_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqw_xor">; +def int_hexagon_A2_satb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; -// -// BUILTIN_INFO(HEXAGON.V6_veqw_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqw_xor_128B -def int_hexagon_V6_veqw_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; +def int_hexagon_C2_cmpltu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth,QV_ftype_VIVI,2) -// tag : V6_vgth -def int_hexagon_V6_vgth : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgth">; +def int_hexagon_S2_insertp : +Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_128B,QV_ftype_VIVI,2) -// tag : V6_vgth_128B -def int_hexagon_V6_vgth_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_128B">; +def int_hexagon_M2_mpyd_rnd_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_and,QV_ftype_QVVIVI,3) -// tag : V6_vgth_and -def int_hexagon_V6_vgth_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_and">; +def int_hexagon_M2_mpyd_rnd_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgth_and_128B -def int_hexagon_V6_vgth_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_and_128B">; +def int_hexagon_S2_lsr_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_or,QV_ftype_QVVIVI,3) -// tag : V6_vgth_or -def int_hexagon_V6_vgth_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_or">; +def int_hexagon_S2_extractup_rp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgth_or_128B -def int_hexagon_V6_vgth_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_or_128B">; +def int_hexagon_S4_vxaddsubw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgth_xor -def int_hexagon_V6_vgth_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgth_xor">; +def int_hexagon_S4_vxaddsubh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; -// -// BUILTIN_INFO(HEXAGON.V6_vgth_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgth_xor_128B -def int_hexagon_V6_vgth_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; +def int_hexagon_A2_asrh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh,QV_ftype_VIVI,2) -// tag : V6_veqh -def int_hexagon_V6_veqh : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqh">; +def int_hexagon_S4_extractp_rp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_128B,QV_ftype_VIVI,2) -// tag : V6_veqh_128B -def int_hexagon_V6_veqh_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_128B">; +def int_hexagon_S2_lsr_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_and,QV_ftype_QVVIVI,3) -// tag : V6_veqh_and -def int_hexagon_V6_veqh_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_and">; +def int_hexagon_M2_mpyd_nac_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqh_and_128B -def int_hexagon_V6_veqh_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_and_128B">; +def int_hexagon_M2_mpyd_nac_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_or,QV_ftype_QVVIVI,3) -// tag : V6_veqh_or -def int_hexagon_V6_veqh_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_or">; +def int_hexagon_C2_or : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqh_or_128B -def int_hexagon_V6_veqh_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_or_128B">; +def int_hexagon_M2_mmpyul_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_xor,QV_ftype_QVVIVI,3) -// tag : V6_veqh_xor -def int_hexagon_V6_veqh_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqh_xor">; +def int_hexagon_M2_vrcmacr_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_veqh_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqh_xor_128B -def int_hexagon_V6_veqh_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; +def int_hexagon_A2_xor : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb,QV_ftype_VIVI,2) -// tag : V6_vgtb -def int_hexagon_V6_vgtb : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtb">; +def int_hexagon_A2_add : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_128B,QV_ftype_VIVI,2) -// tag : V6_vgtb_128B -def int_hexagon_V6_vgtb_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_128B">; +def int_hexagon_A2_vsububs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_and,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_and -def int_hexagon_V6_vgtb_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_and">; +def int_hexagon_M2_vmpy2s_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_and_128B -def int_hexagon_V6_vgtb_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; +def int_hexagon_M2_vmpy2s_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_or,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_or -def int_hexagon_V6_vgtb_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_or">; +def int_hexagon_A2_vraddub_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_or_128B -def int_hexagon_V6_vgtb_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; +def int_hexagon_F2_sfinvsqrta : +Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_xor -def int_hexagon_V6_vgtb_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtb_xor">; +def int_hexagon_S2_ct0p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtb_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtb_xor_128B -def int_hexagon_V6_vgtb_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; +def int_hexagon_A2_svaddh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb,QV_ftype_VIVI,2) -// tag : V6_veqb -def int_hexagon_V6_veqb : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_veqb">; +def int_hexagon_S2_vcrotate : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_128B,QV_ftype_VIVI,2) -// tag : V6_veqb_128B -def int_hexagon_V6_veqb_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_128B">; +def int_hexagon_A2_aslh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_and,QV_ftype_QVVIVI,3) -// tag : V6_veqb_and -def int_hexagon_V6_veqb_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_and">; +def int_hexagon_A2_subh_h16_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqb_and_128B -def int_hexagon_V6_veqb_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_and_128B">; +def int_hexagon_A2_subh_h16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; + +def int_hexagon_M2_hmmpyl_rs1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; + +def int_hexagon_S2_asr_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; + +def int_hexagon_S2_vsplatrh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; + +def int_hexagon_S2_asr_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; + +def int_hexagon_A2_addh_h16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; + +def int_hexagon_S2_vsplatrb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; + +def int_hexagon_A2_addh_h16_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; + +def int_hexagon_M2_cmpyr_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; + +def int_hexagon_M2_dpmpyss_rnd_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; + +def int_hexagon_C2_muxri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri">; + +def int_hexagon_M2_vmac2es_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; + +def int_hexagon_M2_vmac2es_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; + +def int_hexagon_C2_pxfer_map : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; + +def int_hexagon_M2_mpyu_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; + +def int_hexagon_M2_mpyu_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; + +def int_hexagon_S2_asl_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or">; + +def int_hexagon_M2_mpyd_acc_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; + +def int_hexagon_M2_mpyd_acc_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; + +def int_hexagon_S2_asr_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; + +def int_hexagon_A2_vaddw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; + +def int_hexagon_S2_asr_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and">; + +def int_hexagon_A2_vaddh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; + +def int_hexagon_M2_mpy_nac_sat_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; + +def int_hexagon_M2_mpy_nac_sat_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; + +def int_hexagon_C2_cmpeqp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; + +def int_hexagon_M4_mpyri_addi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi">; + +def int_hexagon_A2_not : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; + +def int_hexagon_S4_andi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri">; + +def int_hexagon_M2_macsip : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip">; + +def int_hexagon_A2_tfrcrr : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">; + +def int_hexagon_M2_macsin : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin">; + +def int_hexagon_C2_orn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; + +def int_hexagon_M4_and_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; + +def int_hexagon_F2_sfmpy : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">; + +def int_hexagon_M2_mpyud_nac_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; + +def int_hexagon_M2_mpyud_nac_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; + +def int_hexagon_S2_lsr_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; + +def int_hexagon_S2_asr_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; + +def int_hexagon_M4_and_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; + +def int_hexagon_S2_asr_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; + +def int_hexagon_C2_mask : +Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; + +def int_hexagon_M2_mpy_nac_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; + +def int_hexagon_M2_mpy_nac_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; + +def int_hexagon_M2_mpy_up_s1_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; + +def int_hexagon_A4_vcmpbgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; + +def int_hexagon_M5_vrmacbsu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; + +def int_hexagon_S2_tableidxw_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">; + +def int_hexagon_A2_vrsadub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; + +def int_hexagon_A2_tfrrcr : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">; + +def int_hexagon_M2_vrcmpys_acc_s1 : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; + +def int_hexagon_F2_dfcmpge : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">; + +def int_hexagon_M2_accii : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii">; + +def int_hexagon_A5_vaddhubs : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; + +def int_hexagon_A2_vmaxw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; + +def int_hexagon_A2_vmaxb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; + +def int_hexagon_A2_vmaxh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; + +def int_hexagon_S2_vsxthw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; + +def int_hexagon_S4_andi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri">; + +def int_hexagon_S2_asl_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac">; + +def int_hexagon_S2_lsl_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; + +def int_hexagon_C2_cmpgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; + +def int_hexagon_F2_conv_df2d_chop : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; + +def int_hexagon_M2_mpyu_nac_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; + +def int_hexagon_M2_mpyu_nac_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; + +def int_hexagon_F2_conv_sf2w : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; + +def int_hexagon_S2_lsr_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; + +def int_hexagon_F2_sfclass : +Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">; + +def int_hexagon_M2_mpyud_acc_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; + +def int_hexagon_M4_xor_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; + +def int_hexagon_S2_addasl_rrri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri">; + +def int_hexagon_M5_vdmpybsu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; + +def int_hexagon_M2_mpyu_nac_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; + +def int_hexagon_M2_mpyu_nac_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; + +def int_hexagon_A2_addi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi">; + +def int_hexagon_A2_addp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; + +def int_hexagon_M2_vmpy2s_s1pack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; + +def int_hexagon_S4_clbpnorm : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; + +def int_hexagon_A4_round_rr_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; + +def int_hexagon_M2_nacci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; + +def int_hexagon_S2_shuffeh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; + +def int_hexagon_S2_lsr_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and">; + +def int_hexagon_M2_mpy_sat_rnd_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; + +def int_hexagon_M2_mpy_sat_rnd_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; + +def int_hexagon_F2_conv_sf2uw : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; + +def int_hexagon_A2_vsubh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; + +def int_hexagon_F2_conv_sf2ud : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; + +def int_hexagon_A2_vsubw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; + +def int_hexagon_A2_vcmpwgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; + +def int_hexagon_M4_xor_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; + +def int_hexagon_F2_conv_sf2uw_chop : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; + +def int_hexagon_S2_asl_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; + +def int_hexagon_S2_vsatwuh_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; + +def int_hexagon_S2_asl_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; + +def int_hexagon_A2_svsubuhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; + +def int_hexagon_M5_vmpybsu : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; + +def int_hexagon_A2_subh_l16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; + +def int_hexagon_C4_and_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; + +def int_hexagon_M2_mpyu_acc_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; + +def int_hexagon_M2_mpyu_acc_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; + +def int_hexagon_S2_lsr_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; + +def int_hexagon_S2_lsr_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; + +def int_hexagon_A4_subp_c : +Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_subp_c">; + +def int_hexagon_A2_vsubhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; + +def int_hexagon_C2_vitpack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; + +def int_hexagon_A2_vavguhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; + +def int_hexagon_S2_vsplicerb : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; + +def int_hexagon_C4_nbitsclr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; + +def int_hexagon_A2_vcmpbgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; + +def int_hexagon_M2_cmpys_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; + +def int_hexagon_M2_cmpys_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; + +def int_hexagon_F2_dfcmpuo : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo">; + +def int_hexagon_S2_shuffob : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; + +def int_hexagon_C2_and : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; + +def int_hexagon_S5_popcountp : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; + +def int_hexagon_S4_extractp : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp">; + +def int_hexagon_S2_cl0 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; + +def int_hexagon_A4_vcmpbgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti">; + +def int_hexagon_M2_mmacls_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; + +def int_hexagon_M2_mmacls_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; + +def int_hexagon_C4_cmpneq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; + +def int_hexagon_M2_vmac2es : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; + +def int_hexagon_M2_vdmacs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; + +def int_hexagon_M2_vdmacs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; + +def int_hexagon_M2_mpyud_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; + +def int_hexagon_M2_mpyud_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; + +def int_hexagon_S2_clb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; + +def int_hexagon_M2_mpy_nac_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; + +def int_hexagon_M2_mpy_nac_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; + +def int_hexagon_M2_mpyd_nac_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; + +def int_hexagon_M2_mpyd_nac_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; + +def int_hexagon_M2_maci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; + +def int_hexagon_A2_vmaxuh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; + +def int_hexagon_A4_bitspliti : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti">; + +def int_hexagon_A2_vmaxub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; + +def int_hexagon_M2_mpyud_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; + +def int_hexagon_M2_mpyud_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; + +def int_hexagon_M2_vrmac_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; + +def int_hexagon_M2_mpy_sat_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; + +def int_hexagon_S2_asl_r_r_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; + +def int_hexagon_F2_conv_sf2d : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; + +def int_hexagon_S2_asr_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; + +def int_hexagon_F2_dfimm_n : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n">; + +def int_hexagon_A4_cmphgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; + +def int_hexagon_F2_dfimm_p : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p">; + +def int_hexagon_M2_mpyud_acc_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; + +def int_hexagon_M2_vcmpy_s1_sat_r : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; + +def int_hexagon_M4_mpyri_addr_u2 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2">; + +def int_hexagon_M2_vcmpy_s1_sat_i : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; + +def int_hexagon_S2_lsl_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; + +def int_hexagon_M5_vrmacbuu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; + +def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax">; + +def int_hexagon_S2_vspliceib : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib">; + +def int_hexagon_M2_dpmpyss_acc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; + +def int_hexagon_M2_cnacs_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; + +def int_hexagon_M2_cnacs_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; + +def int_hexagon_A2_maxu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; + +def int_hexagon_A2_maxp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; + +def int_hexagon_A2_andir : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir">; + +def int_hexagon_F2_sfrecipa : +Hexagon_floati32_floatfloat_Intrinsic<"HEXAGON_F2_sfrecipa">; + +def int_hexagon_A2_combineii : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii">; + +def int_hexagon_A4_orn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; + +def int_hexagon_A4_cmpbgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui">; + +def int_hexagon_S2_lsr_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; + +def int_hexagon_A4_vcmpbeqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi">; + +def int_hexagon_S2_lsl_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; + +def int_hexagon_S2_lsl_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; + +def int_hexagon_A2_or : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; + +def int_hexagon_F2_dfcmpeq : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq">; + +def int_hexagon_C2_cmpeq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; + +def int_hexagon_A2_tfrp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; + +def int_hexagon_C4_and_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; + +def int_hexagon_S2_vsathub_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; + +def int_hexagon_A2_satuh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; + +def int_hexagon_A2_satub : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; + +def int_hexagon_M2_vrcmpys_s1 : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; + +def int_hexagon_S4_or_ori : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori">; + +def int_hexagon_C4_fastcorner9_not : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; + +def int_hexagon_A2_tfrih : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih">; + +def int_hexagon_A2_tfril : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril">; + +def int_hexagon_M4_mpyri_addr : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr">; + +def int_hexagon_S2_vtrunehb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; + +def int_hexagon_A2_vabsw : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; + +def int_hexagon_A2_vabsh : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; + +def int_hexagon_F2_sfsub : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub">; + +def int_hexagon_C2_muxii : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii">; + +def int_hexagon_C2_muxir : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir">; + +def int_hexagon_A2_swiz : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; + +def int_hexagon_S2_asr_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and">; + +def int_hexagon_M2_cmpyrsc_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; + +def int_hexagon_M2_cmpyrsc_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; + +def int_hexagon_A2_vraddub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; + +def int_hexagon_A4_tlbmatch : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; + +def int_hexagon_F2_conv_df2w_chop : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; + +def int_hexagon_A2_and : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; + +def int_hexagon_S2_lsr_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; + +def int_hexagon_M2_mpy_nac_sat_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; + +def int_hexagon_M2_mpy_nac_sat_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; + +def int_hexagon_S4_extract : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract">; + +def int_hexagon_A2_vcmpweq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; + +def int_hexagon_M2_acci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; + +def int_hexagon_S2_lsr_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc">; + +def int_hexagon_S2_lsr_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or">; + +def int_hexagon_F2_conv_ud2sf : +Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; + +def int_hexagon_A2_tfr : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; + +def int_hexagon_S2_asr_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or">; + +def int_hexagon_A2_subri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri">; + +def int_hexagon_A4_vrmaxuw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; + +def int_hexagon_M5_vmpybuu : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; + +def int_hexagon_A4_vrmaxuh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; + +def int_hexagon_S2_asl_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw">; + +def int_hexagon_A2_vavgw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; + +def int_hexagon_S2_brev : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; + +def int_hexagon_A2_vavgh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; + +def int_hexagon_S2_clrbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i">; + +def int_hexagon_S2_asl_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh">; + +def int_hexagon_S2_lsr_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or">; + +def int_hexagon_S2_lsl_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; + +def int_hexagon_M2_mmpyl_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; + +def int_hexagon_M2_mpyud_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; + +def int_hexagon_M2_mmpyl_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; + +def int_hexagon_M2_mmpyl_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; + +def int_hexagon_M2_naccii : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii">; + +def int_hexagon_S2_vrndpackwhs : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; + +def int_hexagon_S2_vtrunewh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; + +def int_hexagon_M2_dpmpyss_nac_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; + +def int_hexagon_M2_mpyd_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; + +def int_hexagon_M2_mpyd_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; + +def int_hexagon_M4_mac_up_s1_sat : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; + +def int_hexagon_S4_vrcrotate_acc : +Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc">; + +def int_hexagon_F2_conv_uw2df : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; + +def int_hexagon_A2_vaddubs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; + +def int_hexagon_S2_asr_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; + +def int_hexagon_A2_orir : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir">; + +def int_hexagon_A2_andp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; + +def int_hexagon_S2_lfsp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; + +def int_hexagon_A2_min : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; + +def int_hexagon_M2_mpysmi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi">; + +def int_hexagon_M2_vcmpy_s0_sat_r : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; + +def int_hexagon_M2_mpyu_acc_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; + +def int_hexagon_M2_mpyu_acc_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; + +def int_hexagon_S2_asr_r_svw_trun : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; + +def int_hexagon_M2_mmpyh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; + +def int_hexagon_M2_mmpyh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; + +def int_hexagon_F2_conv_sf2df : +Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; + +def int_hexagon_S2_vtrunohb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; + +def int_hexagon_F2_conv_sf2d_chop : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; + +def int_hexagon_M2_mpyd_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; + +def int_hexagon_F2_conv_df2w : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; + +def int_hexagon_S5_asrhub_sat : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat">; + +def int_hexagon_S2_asl_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc">; + +def int_hexagon_F2_conv_df2d : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; + +def int_hexagon_M2_mmaculs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; + +def int_hexagon_M2_mmaculs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; + +def int_hexagon_A2_svadduhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; + +def int_hexagon_F2_conv_sf2w_chop : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; + +def int_hexagon_S2_svsathub : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; + +def int_hexagon_M2_mpyd_rnd_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; + +def int_hexagon_M2_mpyd_rnd_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; + +def int_hexagon_S2_setbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; + +def int_hexagon_A2_vavghr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; + +def int_hexagon_F2_sffma_sc : +Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc">; + +def int_hexagon_F2_dfclass : +Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass">; + +def int_hexagon_F2_conv_df2ud : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; + +def int_hexagon_F2_conv_df2uw : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; + +def int_hexagon_M2_cmpyrs_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; + +def int_hexagon_M2_cmpyrs_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; + +def int_hexagon_C4_cmpltei : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei">; + +def int_hexagon_C4_cmplteu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; + +def int_hexagon_A2_vsubb_map : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; + +def int_hexagon_A2_subh_l16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; + +def int_hexagon_S2_asr_i_r_rnd : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd">; + +def int_hexagon_M2_vrmpy_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; + +def int_hexagon_M2_mpyd_rnd_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; + +def int_hexagon_M2_mpyd_rnd_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; + +def int_hexagon_A2_minup : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; + +def int_hexagon_S2_valignrb : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; + +def int_hexagon_S2_asr_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; + +def int_hexagon_M2_mmpyl_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; + +def int_hexagon_M2_vrcmaci_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; + +def int_hexagon_A2_vaddub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; + +def int_hexagon_A2_combine_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; + +def int_hexagon_M5_vdmacbsu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; + +def int_hexagon_A2_combine_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; + +def int_hexagon_M2_mpyud_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; + +def int_hexagon_M2_vrcmpyi_s0c : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; + +def int_hexagon_S2_asr_i_p_rnd : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd">; + +def int_hexagon_A2_addpsat : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; + +def int_hexagon_A2_svaddhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; + +def int_hexagon_S4_ori_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri">; + +def int_hexagon_M2_mpy_sat_rnd_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; + +def int_hexagon_M2_mpy_sat_rnd_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; + +def int_hexagon_A2_vminw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; + +def int_hexagon_A2_vminh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; + +def int_hexagon_M2_vrcmpyr_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; + +def int_hexagon_A2_vminb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; + +def int_hexagon_M2_vcmac_s0_sat_i : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; + +def int_hexagon_M2_mpyud_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; + +def int_hexagon_M2_mpyud_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; + +def int_hexagon_S2_asl_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; + +def int_hexagon_S4_lsli : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli">; + +def int_hexagon_S2_lsl_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; + +def int_hexagon_M2_mpy_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; + +def int_hexagon_M4_vrmpyeh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; + +def int_hexagon_M4_vrmpyeh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; + +def int_hexagon_M2_mpy_nac_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; + +def int_hexagon_M2_mpy_nac_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; + +def int_hexagon_M2_vraddh : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; + +def int_hexagon_C2_tfrrp : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; + +def int_hexagon_M2_mpy_acc_sat_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; + +def int_hexagon_M2_mpy_acc_sat_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; + +def int_hexagon_S2_vtrunowh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; + +def int_hexagon_A2_abs : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; + +def int_hexagon_A4_cmpbeq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; + +def int_hexagon_A2_negp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; + +def int_hexagon_S2_asl_i_r_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat">; + +def int_hexagon_A2_addh_l16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; + +def int_hexagon_S2_vsatwuh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; + +def int_hexagon_F2_dfcmpgt : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt">; + +def int_hexagon_S2_svsathb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; + +def int_hexagon_C2_cmpgtup : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; + +def int_hexagon_A4_cround_ri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri">; + +def int_hexagon_S4_clbpaddi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi">; + +def int_hexagon_A4_cround_rr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; + +def int_hexagon_C2_mux : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; + +def int_hexagon_M2_dpmpyuu_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; + +def int_hexagon_S2_shuffeb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; + +def int_hexagon_A2_vminuw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; + +def int_hexagon_A2_vaddhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; + +def int_hexagon_S2_insert_rp : +Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; + +def int_hexagon_A2_vminuh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; + +def int_hexagon_A2_vminub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; + +def int_hexagon_S2_extractu : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu">; + +def int_hexagon_A2_svsubh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; + +def int_hexagon_S4_clbaddi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi">; + +def int_hexagon_F2_sffms : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms">; + +def int_hexagon_S2_vsxtbh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; + +def int_hexagon_M2_mpyud_nac_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; + +def int_hexagon_M2_mpyud_nac_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; + +def int_hexagon_A2_subp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; + +def int_hexagon_M2_vmpy2es_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; + +def int_hexagon_M2_vmpy2es_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; + +def int_hexagon_S4_parity : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; + +def int_hexagon_M2_mpy_acc_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; + +def int_hexagon_M2_mpy_acc_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; + +def int_hexagon_S4_addi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri">; + +def int_hexagon_M2_mpyd_nac_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; + +def int_hexagon_M2_mpyd_nac_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; + +def int_hexagon_S2_asr_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac">; + +def int_hexagon_A4_cmpheqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi">; + +def int_hexagon_S2_lsr_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; + +def int_hexagon_M2_mpy_acc_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; + +def int_hexagon_M2_mpy_acc_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; + +def int_hexagon_F2_conv_sf2ud_chop : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; + +def int_hexagon_C2_cmpgeui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui">; + +def int_hexagon_M2_mpy_acc_sat_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; + +def int_hexagon_M2_mpy_acc_sat_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; + +def int_hexagon_S2_asl_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; + +def int_hexagon_A2_addh_h16_sat_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; + +def int_hexagon_A2_addh_h16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; + +def int_hexagon_M4_nac_up_s1_sat : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; + +def int_hexagon_M2_mpyud_nac_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; + +def int_hexagon_M2_mpyud_nac_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; + +def int_hexagon_A4_round_ri_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat">; + +def int_hexagon_M2_mpy_nac_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; + +def int_hexagon_M2_mpy_nac_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; + +def int_hexagon_A2_vavghcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; + +def int_hexagon_M2_mmacls_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; + +def int_hexagon_M2_mmacls_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; + +def int_hexagon_M2_cmaci_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; + +def int_hexagon_S2_setbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i">; + +def int_hexagon_S2_asl_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or">; + +def int_hexagon_A4_andn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; + +def int_hexagon_M5_vrmpybsu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; + +def int_hexagon_S2_vrndpackwh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; + +def int_hexagon_M2_vcmac_s0_sat_r : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; + +def int_hexagon_A2_vmaxuw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; + +def int_hexagon_C2_bitsclr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; + +def int_hexagon_M2_xor_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; + +def int_hexagon_A4_vcmpbgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui">; + +def int_hexagon_A4_ornp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; + +def int_hexagon_A2_tfrpi : +Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi">; + +def int_hexagon_C4_and_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; + +def int_hexagon_M2_mpy_nac_sat_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; + +def int_hexagon_M2_mpy_nac_sat_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; + +def int_hexagon_A2_subh_h16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; + +def int_hexagon_A2_subh_h16_sat_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; + +def int_hexagon_M2_vmpy2su_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; + +def int_hexagon_M2_vmpy2su_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; + +def int_hexagon_S2_asr_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc">; + +def int_hexagon_C4_nbitsclri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri">; + +def int_hexagon_S2_lsr_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh">; + +def int_hexagon_S2_lsr_i_p_xacc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc">; + +// V55 Scalar Instructions. + +def int_hexagon_A5_ACS : +Hexagon_i64i32_i64i64i64_Intrinsic<"HEXAGON_A5_ACS">; + +// V60 Scalar Instructions. + +def int_hexagon_S6_rol_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and">; + +def int_hexagon_S6_rol_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc">; + +def int_hexagon_S6_rol_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and">; + +def int_hexagon_S6_rol_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc">; + +def int_hexagon_S6_rol_i_p_xacc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc">; + +def int_hexagon_S6_rol_i_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p">; + +def int_hexagon_S6_rol_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac">; + +def int_hexagon_S6_rol_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc">; + +def int_hexagon_S6_rol_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or">; + +def int_hexagon_S6_rol_i_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r">; + +def int_hexagon_S6_rol_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac">; + +def int_hexagon_S6_rol_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or">; + +// V62 Scalar Instructions. + +def int_hexagon_S6_vtrunehb_ppp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; + +def int_hexagon_V6_ldntnt0 : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldntnt0">; + +def int_hexagon_M6_vabsdiffub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; + +def int_hexagon_S6_vtrunohb_ppp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; + +def int_hexagon_M6_vabsdiffb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; + +def int_hexagon_A6_vminub_RdP : +Hexagon_i64i32_i64i64_Intrinsic<"HEXAGON_A6_vminub_RdP">; + +def int_hexagon_S6_vsplatrbp : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; + +// V65 Scalar Instructions. + +def int_hexagon_A6_vcmpbeq_notany : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; + +// V60 HVX Instructions. -// -// BUILTIN_INFO(HEXAGON.V6_veqb_or,QV_ftype_QVVIVI,3) -// tag : V6_veqb_or def int_hexagon_V6_veqb_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_or">; +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqb_or_128B def int_hexagon_V6_veqb_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_or_128B">; +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_xor,QV_ftype_QVVIVI,3) -// tag : V6_veqb_xor -def int_hexagon_V6_veqb_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_veqb_xor">; +def int_hexagon_V6_vminub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; -// -// BUILTIN_INFO(HEXAGON.V6_veqb_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_veqb_xor_128B -def int_hexagon_V6_veqb_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; +def int_hexagon_V6_vminub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw,QV_ftype_VIVI,2) -// tag : V6_vgtuw -def int_hexagon_V6_vgtuw : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw">; +def int_hexagon_V6_vaslw_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_128B,QV_ftype_VIVI,2) -// tag : V6_vgtuw_128B -def int_hexagon_V6_vgtuw_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_128B">; +def int_hexagon_V6_vaslw_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_and,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_and -def int_hexagon_V6_vgtuw_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_and">; +def int_hexagon_V6_vmpyhvsrs : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_and_128B -def int_hexagon_V6_vgtuw_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; +def int_hexagon_V6_vmpyhvsrs_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_or,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_or -def int_hexagon_V6_vgtuw_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_or">; +def int_hexagon_V6_vsathub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_or_128B -def int_hexagon_V6_vgtuw_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; +def int_hexagon_V6_vsathub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_xor -def int_hexagon_V6_vgtuw_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuw_xor">; +def int_hexagon_V6_vaddh_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuw_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuw_xor_128B -def int_hexagon_V6_vgtuw_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; +def int_hexagon_V6_vaddh_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh,QV_ftype_VIVI,2) -// tag : V6_vgtuh -def int_hexagon_V6_vgtuh : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh">; +def int_hexagon_V6_vrmpybusi : +Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_128B,QV_ftype_VIVI,2) -// tag : V6_vgtuh_128B -def int_hexagon_V6_vgtuh_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_128B">; +def int_hexagon_V6_vrmpybusi_128B : +Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B">; + +def int_hexagon_V6_vshufoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; + +def int_hexagon_V6_vshufoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; + +def int_hexagon_V6_vasrwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; + +def int_hexagon_V6_vasrwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; + +def int_hexagon_V6_vdmpyhsuisat : +Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; + +def int_hexagon_V6_vdmpyhsuisat_128B : +Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; + +def int_hexagon_V6_vrsadubi_acc : +Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc">; + +def int_hexagon_V6_vrsadubi_acc_128B : +Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B">; + +def int_hexagon_V6_vnavgw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; + +def int_hexagon_V6_vnavgw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; + +def int_hexagon_V6_vnavgh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; + +def int_hexagon_V6_vnavgh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; + +def int_hexagon_V6_vavgub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; + +def int_hexagon_V6_vavgub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; + +def int_hexagon_V6_vsubb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; + +def int_hexagon_V6_vsubb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; + +def int_hexagon_V6_vgtw_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">; + +def int_hexagon_V6_vgtw_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; + +def int_hexagon_V6_vavgubrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; + +def int_hexagon_V6_vavgubrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; + +def int_hexagon_V6_vrmpybusv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; + +def int_hexagon_V6_vrmpybusv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; + +def int_hexagon_V6_vsubbnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">; + +def int_hexagon_V6_vsubbnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; + +def int_hexagon_V6_vroundhb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; + +def int_hexagon_V6_vroundhb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; + +def int_hexagon_V6_vadduhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; + +def int_hexagon_V6_vadduhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; + +def int_hexagon_V6_vsububsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; + +def int_hexagon_V6_vsububsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; + +def int_hexagon_V6_vmpabus_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; + +def int_hexagon_V6_vmpabus_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; + +def int_hexagon_V6_vmux : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">; + +def int_hexagon_V6_vmux_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">; + +def int_hexagon_V6_vmpyhus : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; + +def int_hexagon_V6_vmpyhus_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; + +def int_hexagon_V6_vpackeb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; + +def int_hexagon_V6_vpackeb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; + +def int_hexagon_V6_vsubhnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">; + +def int_hexagon_V6_vsubhnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; + +def int_hexagon_V6_vavghrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; + +def int_hexagon_V6_vavghrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; + +def int_hexagon_V6_vtran2x2_map : +Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map">; + +def int_hexagon_V6_vtran2x2_map_128B : +Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtran2x2_map_128B">; + +def int_hexagon_V6_vdelta : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; + +def int_hexagon_V6_vdelta_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_and,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_and def int_hexagon_V6_vgtuh_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_and">; +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_and_128B def int_hexagon_V6_vgtuh_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_or,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_or -def int_hexagon_V6_vgtuh_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_or">; +def int_hexagon_V6_vtmpyhb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_or_128B -def int_hexagon_V6_vgtuh_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; +def int_hexagon_V6_vtmpyhb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_xor -def int_hexagon_V6_vgtuh_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtuh_xor">; +def int_hexagon_V6_vpackob : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtuh_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtuh_xor_128B -def int_hexagon_V6_vgtuh_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; +def int_hexagon_V6_vpackob_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub,QV_ftype_VIVI,2) -// tag : V6_vgtub -def int_hexagon_V6_vgtub : -Hexagon_v64iv512v512_Intrinsic<"HEXAGON_V6_vgtub">; +def int_hexagon_V6_vmaxh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_128B,QV_ftype_VIVI,2) -// tag : V6_vgtub_128B -def int_hexagon_V6_vgtub_128B : -Hexagon_v128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_128B">; +def int_hexagon_V6_vmaxh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_and,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_and -def int_hexagon_V6_vgtub_and : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_and">; +def int_hexagon_V6_vtmpybus_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_and_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_and_128B -def int_hexagon_V6_vgtub_and_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; +def int_hexagon_V6_vtmpybus_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_or,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_or -def int_hexagon_V6_vgtub_or : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_or">; +def int_hexagon_V6_vsubuhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_or_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_or_128B -def int_hexagon_V6_vgtub_or_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; +def int_hexagon_V6_vsubuhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_xor,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_xor -def int_hexagon_V6_vgtub_xor : -Hexagon_v64iv64iv512v512_Intrinsic<"HEXAGON_V6_vgtub_xor">; +def int_hexagon_V6_vasrw_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vgtub_xor_128B,QV_ftype_QVVIVI,3) -// tag : V6_vgtub_xor_128B -def int_hexagon_V6_vgtub_xor_128B : -Hexagon_v128iv128iv1024v1024_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; +def int_hexagon_V6_vasrw_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_or,QV_ftype_QVQV,2) -// tag : V6_pred_or def int_hexagon_V6_pred_or : -Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or">; +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_or_128B,QV_ftype_QVQV,2) -// tag : V6_pred_or_128B def int_hexagon_V6_pred_or_128B : -Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_128B">; +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_and,QV_ftype_QVQV,2) -// tag : V6_pred_and -def int_hexagon_V6_pred_and : -Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and">; +def int_hexagon_V6_vrmpyub_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_and_128B,QV_ftype_QVQV,2) -// tag : V6_pred_and_128B -def int_hexagon_V6_pred_and_128B : -Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_128B">; +def int_hexagon_V6_vrmpyub_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_not,QV_ftype_QV,1) -// tag : V6_pred_not -def int_hexagon_V6_pred_not : -Hexagon_v64iv64i_Intrinsic<"HEXAGON_V6_pred_not">; +def int_hexagon_V6_lo : +Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_not_128B,QV_ftype_QV,1) -// tag : V6_pred_not_128B -def int_hexagon_V6_pred_not_128B : -Hexagon_v128iv128i_Intrinsic<"HEXAGON_V6_pred_not_128B">; +def int_hexagon_V6_lo_128B : +Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_xor,QV_ftype_QVQV,2) -// tag : V6_pred_xor -def int_hexagon_V6_pred_xor : -Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_xor">; +def int_hexagon_V6_vsubb_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_xor_128B,QV_ftype_QVQV,2) -// tag : V6_pred_xor_128B -def int_hexagon_V6_pred_xor_128B : -Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_xor_128B">; +def int_hexagon_V6_vsubb_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; + +def int_hexagon_V6_vsubhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; + +def int_hexagon_V6_vsubhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; + +def int_hexagon_V6_vmpyiwh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; + +def int_hexagon_V6_vmpyiwh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; + +def int_hexagon_V6_vmpyiwb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; + +def int_hexagon_V6_vmpyiwb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; + +def int_hexagon_V6_ldu0 : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldu0">; + +def int_hexagon_V6_ldu0_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldu0_128B">; + +def int_hexagon_V6_vgtuh_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">; + +def int_hexagon_V6_vgtuh_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; + +def int_hexagon_V6_vgth_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">; + +def int_hexagon_V6_vgth_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">; + +def int_hexagon_V6_vavgh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; + +def int_hexagon_V6_vavgh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; + +def int_hexagon_V6_vlalignb : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; + +def int_hexagon_V6_vlalignb_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; + +def int_hexagon_V6_vsh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; + +def int_hexagon_V6_vsh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_and_n,QV_ftype_QVQV,2) -// tag : V6_pred_and_n def int_hexagon_V6_pred_and_n : -Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_and_n">; +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and_n">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_and_n_128B,QV_ftype_QVQV,2) -// tag : V6_pred_and_n_128B def int_hexagon_V6_pred_and_n_128B : -Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_or_n,QV_ftype_QVQV,2) -// tag : V6_pred_or_n -def int_hexagon_V6_pred_or_n : -Hexagon_v64iv64iv64i_Intrinsic<"HEXAGON_V6_pred_or_n">; +def int_hexagon_V6_vsb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_or_n_128B,QV_ftype_QVQV,2) -// tag : V6_pred_or_n_128B -def int_hexagon_V6_pred_or_n_128B : -Hexagon_v128iv128iv128i_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; +def int_hexagon_V6_vsb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_scalar2,QV_ftype_SI,1) -// tag : V6_pred_scalar2 -def int_hexagon_V6_pred_scalar2 : -Hexagon_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2">; +def int_hexagon_V6_vroundwuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_scalar2_128B,QV_ftype_SI,1) -// tag : V6_pred_scalar2_128B -def int_hexagon_V6_pred_scalar2_128B : -Hexagon_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; +def int_hexagon_V6_vroundwuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmux,VI_ftype_QVVIVI,3) -// tag : V6_vmux -def int_hexagon_V6_vmux : -Hexagon_v512v64iv512v512_Intrinsic<"HEXAGON_V6_vmux">; +def int_hexagon_V6_vasrhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; -// -// BUILTIN_INFO(HEXAGON.V6_vmux_128B,VI_ftype_QVVIVI,3) -// tag : V6_vmux_128B -def int_hexagon_V6_vmux_128B : -Hexagon_v1024v128iv1024v1024_Intrinsic<"HEXAGON_V6_vmux_128B">; +def int_hexagon_V6_vasrhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vswap,VD_ftype_QVVIVI,3) -// tag : V6_vswap -def int_hexagon_V6_vswap : -Hexagon_v1024v64iv512v512_Intrinsic<"HEXAGON_V6_vswap">; +def int_hexagon_V6_vshuffh : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; -// -// BUILTIN_INFO(HEXAGON.V6_vswap_128B,VD_ftype_QVVIVI,3) -// tag : V6_vswap_128B -def int_hexagon_V6_vswap_128B : -Hexagon_v2048v128iv1024v1024_Intrinsic<"HEXAGON_V6_vswap_128B">; +def int_hexagon_V6_vshuffh_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; + +def int_hexagon_V6_vaddhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; + +def int_hexagon_V6_vaddhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; + +def int_hexagon_V6_vnavgub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; + +def int_hexagon_V6_vnavgub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; + +def int_hexagon_V6_vrmpybv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; + +def int_hexagon_V6_vrmpybv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; + +def int_hexagon_V6_vnormamth : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; + +def int_hexagon_V6_vnormamth_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; + +def int_hexagon_V6_vdmpyhb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; + +def int_hexagon_V6_vdmpyhb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; + +def int_hexagon_V6_vavguh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; + +def int_hexagon_V6_vavguh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; + +def int_hexagon_V6_vlsrwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; + +def int_hexagon_V6_vlsrwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; + +def int_hexagon_V6_vlsrhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; + +def int_hexagon_V6_vlsrhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; + +def int_hexagon_V6_vdmpyhisat : +Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; + +def int_hexagon_V6_vdmpyhisat_128B : +Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; + +def int_hexagon_V6_vdmpyhvsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; + +def int_hexagon_V6_vdmpyhvsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; + +def int_hexagon_V6_vaddw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; + +def int_hexagon_V6_vaddw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; + +def int_hexagon_V6_vzh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; + +def int_hexagon_V6_vzh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; + +def int_hexagon_V6_vaddh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; + +def int_hexagon_V6_vaddh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxub,VI_ftype_VIVI,2) -// tag : V6_vmaxub def int_hexagon_V6_vmaxub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxub">; +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxub_128B,VI_ftype_VIVI,2) -// tag : V6_vmaxub_128B def int_hexagon_V6_vmaxub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxub_128B">; +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vminub,VI_ftype_VIVI,2) -// tag : V6_vminub -def int_hexagon_V6_vminub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminub">; +def int_hexagon_V6_vmpyhv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vminub_128B,VI_ftype_VIVI,2) -// tag : V6_vminub_128B -def int_hexagon_V6_vminub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminub_128B">; +def int_hexagon_V6_vmpyhv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxuh,VI_ftype_VIVI,2) -// tag : V6_vmaxuh -def int_hexagon_V6_vmaxuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxuh">; +def int_hexagon_V6_vadduhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxuh_128B,VI_ftype_VIVI,2) -// tag : V6_vmaxuh_128B -def int_hexagon_V6_vmaxuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; +def int_hexagon_V6_vadduhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; + +def int_hexagon_V6_vshufoeh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; + +def int_hexagon_V6_vshufoeh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; + +def int_hexagon_V6_vmpyuhv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; + +def int_hexagon_V6_vmpyuhv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; + +def int_hexagon_V6_veqh : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">; + +def int_hexagon_V6_veqh_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">; + +def int_hexagon_V6_vmpabuuv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; + +def int_hexagon_V6_vmpabuuv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; + +def int_hexagon_V6_vasrwhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; + +def int_hexagon_V6_vasrwhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vminuh,VI_ftype_VIVI,2) -// tag : V6_vminuh def int_hexagon_V6_vminuh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminuh">; +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; -// -// BUILTIN_INFO(HEXAGON.V6_vminuh_128B,VI_ftype_VIVI,2) -// tag : V6_vminuh_128B def int_hexagon_V6_vminuh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminuh_128B">; +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxh,VI_ftype_VIVI,2) -// tag : V6_vmaxh -def int_hexagon_V6_vmaxh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxh">; +def int_hexagon_V6_vror : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxh_128B,VI_ftype_VIVI,2) -// tag : V6_vmaxh_128B -def int_hexagon_V6_vmaxh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxh_128B">; +def int_hexagon_V6_vror_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vminh,VI_ftype_VIVI,2) -// tag : V6_vminh -def int_hexagon_V6_vminh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminh">; +def int_hexagon_V6_vmpyowh_rnd_sacc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; -// -// BUILTIN_INFO(HEXAGON.V6_vminh_128B,VI_ftype_VIVI,2) -// tag : V6_vminh_128B -def int_hexagon_V6_vminh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminh_128B">; +def int_hexagon_V6_vmpyowh_rnd_sacc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxw,VI_ftype_VIVI,2) -// tag : V6_vmaxw -def int_hexagon_V6_vmaxw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxw">; +def int_hexagon_V6_vmaxuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxw_128B,VI_ftype_VIVI,2) -// tag : V6_vmaxw_128B -def int_hexagon_V6_vmaxw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxw_128B">; +def int_hexagon_V6_vmaxuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vminw,VI_ftype_VIVI,2) -// tag : V6_vminw -def int_hexagon_V6_vminw : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vminw">; +def int_hexagon_V6_vabsh_sat : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vminw_128B,VI_ftype_VIVI,2) -// tag : V6_vminw_128B -def int_hexagon_V6_vminw_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminw_128B">; +def int_hexagon_V6_vabsh_sat_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsathub,VI_ftype_VIVI,2) -// tag : V6_vsathub -def int_hexagon_V6_vsathub : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsathub">; +def int_hexagon_V6_pred_or_n : +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_or_n">; -// -// BUILTIN_INFO(HEXAGON.V6_vsathub_128B,VI_ftype_VIVI,2) -// tag : V6_vsathub_128B -def int_hexagon_V6_vsathub_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsathub_128B">; +def int_hexagon_V6_pred_or_n_128B : +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsatwh,VI_ftype_VIVI,2) -// tag : V6_vsatwh -def int_hexagon_V6_vsatwh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vsatwh">; +def int_hexagon_V6_vdealb : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; -// -// BUILTIN_INFO(HEXAGON.V6_vsatwh_128B,VI_ftype_VIVI,2) -// tag : V6_vsatwh_128B -def int_hexagon_V6_vsatwh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatwh_128B">; +def int_hexagon_V6_vdealb_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffeb,VI_ftype_VIVI,2) -// tag : V6_vshuffeb -def int_hexagon_V6_vshuffeb : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffeb">; +def int_hexagon_V6_vmpybusv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffeb_128B,VI_ftype_VIVI,2) -// tag : V6_vshuffeb_128B -def int_hexagon_V6_vshuffeb_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; +def int_hexagon_V6_vmpybusv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffob,VI_ftype_VIVI,2) -// tag : V6_vshuffob -def int_hexagon_V6_vshuffob : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshuffob">; +def int_hexagon_V6_vzb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffob_128B,VI_ftype_VIVI,2) -// tag : V6_vshuffob_128B -def int_hexagon_V6_vshuffob_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshuffob_128B">; +def int_hexagon_V6_vzb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufeh,VI_ftype_VIVI,2) -// tag : V6_vshufeh -def int_hexagon_V6_vshufeh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufeh">; +def int_hexagon_V6_vdmpybus_dv : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufeh_128B,VI_ftype_VIVI,2) -// tag : V6_vshufeh_128B -def int_hexagon_V6_vshufeh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufeh_128B">; +def int_hexagon_V6_vdmpybus_dv_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoh,VI_ftype_VIVI,2) -// tag : V6_vshufoh -def int_hexagon_V6_vshufoh : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vshufoh">; +def int_hexagon_V6_vaddbq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoh_128B,VI_ftype_VIVI,2) -// tag : V6_vshufoh_128B -def int_hexagon_V6_vshufoh_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vshufoh_128B">; +def int_hexagon_V6_vaddbq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffvdd,VD_ftype_VIVISI,3) -// tag : V6_vshuffvdd -def int_hexagon_V6_vshuffvdd : -Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vshuffvdd">; +def int_hexagon_V6_vaddb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffvdd_128B,VD_ftype_VIVISI,3) -// tag : V6_vshuffvdd_128B -def int_hexagon_V6_vshuffvdd_128B : -Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; +def int_hexagon_V6_vaddb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealvdd,VD_ftype_VIVISI,3) -// tag : V6_vdealvdd -def int_hexagon_V6_vdealvdd : -Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vdealvdd">; +def int_hexagon_V6_vaddwq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealvdd_128B,VD_ftype_VIVISI,3) -// tag : V6_vdealvdd_128B -def int_hexagon_V6_vdealvdd_128B : -Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; +def int_hexagon_V6_vaddwq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoeh,VD_ftype_VIVI,2) -// tag : V6_vshufoeh -def int_hexagon_V6_vshufoeh : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeh">; +def int_hexagon_V6_vasrhubrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoeh_128B,VD_ftype_VIVI,2) -// tag : V6_vshufoeh_128B -def int_hexagon_V6_vshufoeh_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; +def int_hexagon_V6_vasrhubrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; + +def int_hexagon_V6_vasrhubsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; + +def int_hexagon_V6_vasrhubsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoeb,VD_ftype_VIVI,2) -// tag : V6_vshufoeb def int_hexagon_V6_vshufoeb : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vshufoeb">; +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; -// -// BUILTIN_INFO(HEXAGON.V6_vshufoeb_128B,VD_ftype_VIVI,2) -// tag : V6_vshufoeb_128B def int_hexagon_V6_vshufoeb_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealh,VI_ftype_VI,1) -// tag : V6_vdealh -def int_hexagon_V6_vdealh : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealh">; +def int_hexagon_V6_vpackhub_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealh_128B,VI_ftype_VI,1) -// tag : V6_vdealh_128B -def int_hexagon_V6_vdealh_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealh_128B">; +def int_hexagon_V6_vpackhub_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealb,VI_ftype_VI,1) -// tag : V6_vdealb -def int_hexagon_V6_vdealb : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vdealb">; +def int_hexagon_V6_vmpyiwh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealb_128B,VI_ftype_VI,1) -// tag : V6_vdealb_128B -def int_hexagon_V6_vdealb_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vdealb_128B">; +def int_hexagon_V6_vmpyiwh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealb4w,VI_ftype_VIVI,2) -// tag : V6_vdealb4w -def int_hexagon_V6_vdealb4w : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdealb4w">; +def int_hexagon_V6_vtmpyb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; -// -// BUILTIN_INFO(HEXAGON.V6_vdealb4w_128B,VI_ftype_VIVI,2) -// tag : V6_vdealb4w_128B -def int_hexagon_V6_vdealb4w_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; +def int_hexagon_V6_vtmpyb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffh,VI_ftype_VI,1) -// tag : V6_vshuffh -def int_hexagon_V6_vshuffh : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffh">; +def int_hexagon_V6_vmpabusv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffh_128B,VI_ftype_VI,1) -// tag : V6_vshuffh_128B -def int_hexagon_V6_vshuffh_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffh_128B">; +def int_hexagon_V6_vmpabusv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffb,VI_ftype_VI,1) -// tag : V6_vshuffb -def int_hexagon_V6_vshuffb : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vshuffb">; +def int_hexagon_V6_pred_and : +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vshuffb_128B,VI_ftype_VI,1) -// tag : V6_vshuffb_128B -def int_hexagon_V6_vshuffb_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vshuffb_128B">; +def int_hexagon_V6_pred_and_128B : +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_and_128B">; + +def int_hexagon_V6_vsubwnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">; + +def int_hexagon_V6_vsubwnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; + +def int_hexagon_V6_vpackwuh_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; + +def int_hexagon_V6_vpackwuh_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; + +def int_hexagon_V6_vswap : +Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">; + +def int_hexagon_V6_vswap_128B : +Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">; + +def int_hexagon_V6_vrmpyubv_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; + +def int_hexagon_V6_vrmpyubv_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; + +def int_hexagon_V6_vgtb_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">; + +def int_hexagon_V6_vgtb_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; + +def int_hexagon_V6_vaslw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; + +def int_hexagon_V6_vaslw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; + +def int_hexagon_V6_vpackhb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; + +def int_hexagon_V6_vpackhb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; + +def int_hexagon_V6_vmpyih_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; + +def int_hexagon_V6_vmpyih_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; + +def int_hexagon_V6_vshuffvdd : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; + +def int_hexagon_V6_vshuffvdd_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; + +def int_hexagon_V6_vaddb_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; + +def int_hexagon_V6_vaddb_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; + +def int_hexagon_V6_vunpackub : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; + +def int_hexagon_V6_vunpackub_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; + +def int_hexagon_V6_vgtuw : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">; + +def int_hexagon_V6_vgtuw_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">; + +def int_hexagon_V6_vlutvwh : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; + +def int_hexagon_V6_vlutvwh_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; + +def int_hexagon_V6_vgtub : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">; + +def int_hexagon_V6_vgtub_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">; + +def int_hexagon_V6_vmpyowh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; + +def int_hexagon_V6_vmpyowh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; + +def int_hexagon_V6_vmpyieoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; + +def int_hexagon_V6_vmpyieoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_extractw,SI_ftype_VISI,2) -// tag : V6_extractw def int_hexagon_V6_extractw : -Hexagon_iv512i_Intrinsic<"HEXAGON_V6_extractw">; +Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; -// -// BUILTIN_INFO(HEXAGON.V6_extractw_128B,SI_ftype_VISI,2) -// tag : V6_extractw_128B def int_hexagon_V6_extractw_128B : -Hexagon_iv1024i_Intrinsic<"HEXAGON_V6_extractw_128B">; +Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vinsertwr,VI_ftype_VISI,2) -// tag : V6_vinsertwr -def int_hexagon_V6_vinsertwr : -Hexagon_v512v512i_Intrinsic<"HEXAGON_V6_vinsertwr">; +def int_hexagon_V6_vavgwrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; -// -// BUILTIN_INFO(HEXAGON.V6_vinsertwr_128B,VI_ftype_VISI,2) -// tag : V6_vinsertwr_128B -def int_hexagon_V6_vinsertwr_128B : -Hexagon_v1024v1024i_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; +def int_hexagon_V6_vavgwrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplatw,VI_ftype_SI,1) -// tag : V6_lvsplatw -def int_hexagon_V6_lvsplatw : -Hexagon_v512i_Intrinsic<"HEXAGON_V6_lvsplatw">; +def int_hexagon_V6_vdmpyhsat_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplatw_128B,VI_ftype_SI,1) -// tag : V6_lvsplatw_128B -def int_hexagon_V6_lvsplatw_128B : -Hexagon_v1024i_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; +def int_hexagon_V6_vdmpyhsat_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vassign,VI_ftype_VI,1) -// tag : V6_vassign -def int_hexagon_V6_vassign : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vassign">; +def int_hexagon_V6_vgtub_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vassign_128B,VI_ftype_VI,1) -// tag : V6_vassign_128B -def int_hexagon_V6_vassign_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vassign_128B">; +def int_hexagon_V6_vgtub_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; + +def int_hexagon_V6_vmpyub : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; + +def int_hexagon_V6_vmpyub_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; + +def int_hexagon_V6_vmpyuh : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; + +def int_hexagon_V6_vmpyuh_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; + +def int_hexagon_V6_vunpackob : +Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; + +def int_hexagon_V6_vunpackob_128B : +Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; + +def int_hexagon_V6_vmpahb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; + +def int_hexagon_V6_vmpahb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; + +def int_hexagon_V6_veqw_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">; + +def int_hexagon_V6_veqw_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">; + +def int_hexagon_V6_vandqrt : +Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt">; + +def int_hexagon_V6_vandqrt_128B : +Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">; + +def int_hexagon_V6_vxor : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; + +def int_hexagon_V6_vxor_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; + +def int_hexagon_V6_vasrwhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; + +def int_hexagon_V6_vasrwhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; + +def int_hexagon_V6_vmpyhsat_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; + +def int_hexagon_V6_vmpyhsat_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; + +def int_hexagon_V6_vrmpybus_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; + +def int_hexagon_V6_vrmpybus_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; + +def int_hexagon_V6_vsubhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; + +def int_hexagon_V6_vsubhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; + +def int_hexagon_V6_vdealb4w : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; + +def int_hexagon_V6_vdealb4w_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; + +def int_hexagon_V6_vmpyowh_sacc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; + +def int_hexagon_V6_vmpyowh_sacc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; + +def int_hexagon_V6_vmpybv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; + +def int_hexagon_V6_vmpybv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; + +def int_hexagon_V6_vabsdiffh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; + +def int_hexagon_V6_vabsdiffh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; + +def int_hexagon_V6_vshuffob : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; + +def int_hexagon_V6_vshuffob_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; + +def int_hexagon_V6_vmpyub_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; + +def int_hexagon_V6_vmpyub_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; + +def int_hexagon_V6_vnormamtw : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; + +def int_hexagon_V6_vnormamtw_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; + +def int_hexagon_V6_vunpackuh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; + +def int_hexagon_V6_vunpackuh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; + +def int_hexagon_V6_vgtuh_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">; + +def int_hexagon_V6_vgtuh_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; + +def int_hexagon_V6_vmpyiewuh_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; + +def int_hexagon_V6_vmpyiewuh_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; + +def int_hexagon_V6_vunpackoh : +Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; + +def int_hexagon_V6_vunpackoh_128B : +Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; + +def int_hexagon_V6_vdmpyhsat : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; + +def int_hexagon_V6_vdmpyhsat_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; + +def int_hexagon_V6_vmpyubv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; + +def int_hexagon_V6_vmpyubv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; + +def int_hexagon_V6_vmpyhss : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; + +def int_hexagon_V6_vmpyhss_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; + +def int_hexagon_V6_hi : +Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; + +def int_hexagon_V6_hi_128B : +Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; + +def int_hexagon_V6_vasrwuhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; + +def int_hexagon_V6_vasrwuhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; + +def int_hexagon_V6_veqw : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">; + +def int_hexagon_V6_veqw_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">; + +def int_hexagon_V6_vdsaduh : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; + +def int_hexagon_V6_vdsaduh_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; + +def int_hexagon_V6_vsubw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; + +def int_hexagon_V6_vsubw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; + +def int_hexagon_V6_vsubw_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; + +def int_hexagon_V6_vsubw_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; + +def int_hexagon_V6_veqb_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">; + +def int_hexagon_V6_veqb_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">; + +def int_hexagon_V6_vmpyih : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; + +def int_hexagon_V6_vmpyih_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; + +def int_hexagon_V6_vtmpyb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; + +def int_hexagon_V6_vtmpyb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; + +def int_hexagon_V6_vrmpybus : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; + +def int_hexagon_V6_vrmpybus_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; + +def int_hexagon_V6_vmpybus_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; + +def int_hexagon_V6_vmpybus_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; + +def int_hexagon_V6_vgth_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">; + +def int_hexagon_V6_vgth_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; + +def int_hexagon_V6_vsubhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; + +def int_hexagon_V6_vsubhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; + +def int_hexagon_V6_vrmpyubi_acc : +Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc">; + +def int_hexagon_V6_vrmpyubi_acc_128B : +Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B">; + +def int_hexagon_V6_vabsw : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; + +def int_hexagon_V6_vabsw_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; + +def int_hexagon_V6_vaddwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; + +def int_hexagon_V6_vaddwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; + +def int_hexagon_V6_vlsrw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; + +def int_hexagon_V6_vlsrw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; + +def int_hexagon_V6_vabsh : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; + +def int_hexagon_V6_vabsh_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; + +def int_hexagon_V6_vlsrh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; + +def int_hexagon_V6_vlsrh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; + +def int_hexagon_V6_valignb : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; + +def int_hexagon_V6_valignb_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; + +def int_hexagon_V6_vsubhq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">; + +def int_hexagon_V6_vsubhq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">; + +def int_hexagon_V6_vpackoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; + +def int_hexagon_V6_vpackoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; + +def int_hexagon_V6_vdmpybus_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; + +def int_hexagon_V6_vdmpybus_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; + +def int_hexagon_V6_vdmpyhvsat_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; + +def int_hexagon_V6_vdmpyhvsat_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; + +def int_hexagon_V6_vrmpybv_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; + +def int_hexagon_V6_vrmpybv_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; + +def int_hexagon_V6_vaddhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; + +def int_hexagon_V6_vaddhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vcombine,VD_ftype_VIVI,2) -// tag : V6_vcombine def int_hexagon_V6_vcombine : -Hexagon_v1024v512v512_Intrinsic<"HEXAGON_V6_vcombine">; +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; -// -// BUILTIN_INFO(HEXAGON.V6_vcombine_128B,VD_ftype_VIVI,2) -// tag : V6_vcombine_128B def int_hexagon_V6_vcombine_128B : -Hexagon_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vcombine_128B">; +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdelta,VI_ftype_VIVI,2) -// tag : V6_vdelta -def int_hexagon_V6_vdelta : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vdelta">; +def int_hexagon_V6_vandqrt_acc : +Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vdelta_128B,VI_ftype_VIVI,2) -// tag : V6_vdelta_128B -def int_hexagon_V6_vdelta_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vdelta_128B">; +def int_hexagon_V6_vandqrt_acc_128B : +Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrdelta,VI_ftype_VIVI,2) -// tag : V6_vrdelta -def int_hexagon_V6_vrdelta : -Hexagon_v512v512v512_Intrinsic<"HEXAGON_V6_vrdelta">; +def int_hexagon_V6_vaslhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; -// -// BUILTIN_INFO(HEXAGON.V6_vrdelta_128B,VI_ftype_VIVI,2) -// tag : V6_vrdelta_128B -def int_hexagon_V6_vrdelta_128B : -Hexagon_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrdelta_128B">; +def int_hexagon_V6_vaslhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vcl0w,VI_ftype_VI,1) -// tag : V6_vcl0w -def int_hexagon_V6_vcl0w : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0w">; +def int_hexagon_V6_vinsertwr : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; -// -// BUILTIN_INFO(HEXAGON.V6_vcl0w_128B,VI_ftype_VI,1) -// tag : V6_vcl0w_128B -def int_hexagon_V6_vcl0w_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0w_128B">; +def int_hexagon_V6_vinsertwr_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; + +def int_hexagon_V6_vsubh_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; + +def int_hexagon_V6_vsubh_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; + +def int_hexagon_V6_vshuffb : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; + +def int_hexagon_V6_vshuffb_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; + +def int_hexagon_V6_vand : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; + +def int_hexagon_V6_vand_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; + +def int_hexagon_V6_vmpyhv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; + +def int_hexagon_V6_vmpyhv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; + +def int_hexagon_V6_vdmpyhsuisat_acc : +Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; + +def int_hexagon_V6_vdmpyhsuisat_acc_128B : +Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; + +def int_hexagon_V6_vsububsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; + +def int_hexagon_V6_vsububsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; + +def int_hexagon_V6_vgtb_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">; + +def int_hexagon_V6_vgtb_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; + +def int_hexagon_V6_vdsaduh_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; + +def int_hexagon_V6_vdsaduh_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; + +def int_hexagon_V6_vrmpyub : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; + +def int_hexagon_V6_vrmpyub_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; + +def int_hexagon_V6_vmpyuh_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; + +def int_hexagon_V6_vmpyuh_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vcl0h,VI_ftype_VI,1) -// tag : V6_vcl0h def int_hexagon_V6_vcl0h : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vcl0h">; +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; -// -// BUILTIN_INFO(HEXAGON.V6_vcl0h_128B,VI_ftype_VI,1) -// tag : V6_vcl0h_128B def int_hexagon_V6_vcl0h_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vcl0h_128B">; +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vnormamtw,VI_ftype_VI,1) -// tag : V6_vnormamtw -def int_hexagon_V6_vnormamtw : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamtw">; +def int_hexagon_V6_vmpyhus_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vnormamtw_128B,VI_ftype_VI,1) -// tag : V6_vnormamtw_128B -def int_hexagon_V6_vnormamtw_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; +def int_hexagon_V6_vmpyhus_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vnormamth,VI_ftype_VI,1) -// tag : V6_vnormamth -def int_hexagon_V6_vnormamth : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vnormamth">; +def int_hexagon_V6_vmpybv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vnormamth_128B,VI_ftype_VI,1) -// tag : V6_vnormamth_128B -def int_hexagon_V6_vnormamth_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vnormamth_128B">; +def int_hexagon_V6_vmpybv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; + +def int_hexagon_V6_vrsadubi : +Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi">; + +def int_hexagon_V6_vrsadubi_128B : +Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B">; + +def int_hexagon_V6_vdmpyhb_dv_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; + +def int_hexagon_V6_vdmpyhb_dv_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; + +def int_hexagon_V6_vshufeh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; + +def int_hexagon_V6_vshufeh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; + +def int_hexagon_V6_vmpyewuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; + +def int_hexagon_V6_vmpyewuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; + +def int_hexagon_V6_vmpyhsrs : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; + +def int_hexagon_V6_vmpyhsrs_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; + +def int_hexagon_V6_vdmpybus_dv_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; + +def int_hexagon_V6_vdmpybus_dv_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; + +def int_hexagon_V6_vaddubh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; + +def int_hexagon_V6_vaddubh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; + +def int_hexagon_V6_vasrwh : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; + +def int_hexagon_V6_vasrwh_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; + +def int_hexagon_V6_ld0 : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ld0">; + +def int_hexagon_V6_ld0_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ld0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vpopcounth,VI_ftype_VI,1) -// tag : V6_vpopcounth def int_hexagon_V6_vpopcounth : -Hexagon_v512v512_Intrinsic<"HEXAGON_V6_vpopcounth">; +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; -// -// BUILTIN_INFO(HEXAGON.V6_vpopcounth_128B,VI_ftype_VI,1) -// tag : V6_vpopcounth_128B def int_hexagon_V6_vpopcounth_128B : -Hexagon_v1024v1024_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; + +def int_hexagon_V6_ldnt0 : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_ldnt0">; + +def int_hexagon_V6_ldnt0_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_ldnt0_128B">; + +def int_hexagon_V6_vgth_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">; + +def int_hexagon_V6_vgth_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">; + +def int_hexagon_V6_vaddubsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; + +def int_hexagon_V6_vaddubsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; + +def int_hexagon_V6_vpackeh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; + +def int_hexagon_V6_vpackeh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; + +def int_hexagon_V6_vmpyh : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; + +def int_hexagon_V6_vmpyh_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; + +def int_hexagon_V6_vminh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; + +def int_hexagon_V6_vminh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; + +def int_hexagon_V6_pred_scalar2 : +Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">; + +def int_hexagon_V6_pred_scalar2_128B : +Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; + +def int_hexagon_V6_vdealh : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; + +def int_hexagon_V6_vdealh_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; + +def int_hexagon_V6_vpackwh_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; + +def int_hexagon_V6_vpackwh_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; + +def int_hexagon_V6_vaslh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; + +def int_hexagon_V6_vaslh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; + +def int_hexagon_V6_vgtuw_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">; + +def int_hexagon_V6_vgtuw_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; + +def int_hexagon_V6_vor : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; + +def int_hexagon_V6_vor_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb,VI_ftype_VIVISI,3) -// tag : V6_vlutvvb def int_hexagon_V6_vlutvvb : -Hexagon_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb">; +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_128B,VI_ftype_VIVISI,3) -// tag : V6_vlutvvb_128B def int_hexagon_V6_vlutvvb_128B : -Hexagon_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; + +def int_hexagon_V6_vmpyiowh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; + +def int_hexagon_V6_vmpyiowh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc,VI_ftype_VIVIVISI,4) -// tag : V6_vlutvvb_oracc def int_hexagon_V6_vlutvvb_oracc : -Hexagon_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; +Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracc_128B,VI_ftype_VIVIVISI,4) -// tag : V6_vlutvvb_oracc_128B def int_hexagon_V6_vlutvvb_oracc_128B : -Hexagon_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh,VD_ftype_VIVISI,3) -// tag : V6_vlutvwh -def int_hexagon_V6_vlutvwh : -Hexagon_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh">; +def int_hexagon_V6_vandvrt : +Hexagon_v512i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_128B,VD_ftype_VIVISI,3) -// tag : V6_vlutvwh_128B -def int_hexagon_V6_vlutvwh_128B : -Hexagon_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; +def int_hexagon_V6_vandvrt_128B : +Hexagon_v1024i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc,VD_ftype_VDVIVISI,4) -// tag : V6_vlutvwh_oracc -def int_hexagon_V6_vlutvwh_oracc : -Hexagon_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; +def int_hexagon_V6_veqh_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracc_128B,VD_ftype_VDVIVISI,4) -// tag : V6_vlutvwh_oracc_128B -def int_hexagon_V6_vlutvwh_oracc_128B : -Hexagon_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; +def int_hexagon_V6_veqh_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; -// -// Masked vector stores -// -def int_hexagon_V6_vS32b_qpred_ai : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">; +def int_hexagon_V6_vadduhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; -def int_hexagon_V6_vS32b_nqpred_ai : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">; +def int_hexagon_V6_vadduhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; -def int_hexagon_V6_vS32b_nt_qpred_ai : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">; +def int_hexagon_V6_vcl0w : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; -def int_hexagon_V6_vS32b_nt_nqpred_ai : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">; +def int_hexagon_V6_vcl0w_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; -def int_hexagon_V6_vS32b_qpred_ai_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">; +def int_hexagon_V6_vmpyihb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; -def int_hexagon_V6_vS32b_nqpred_ai_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">; +def int_hexagon_V6_vmpyihb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; -def int_hexagon_V6_vS32b_nt_qpred_ai_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">; +def int_hexagon_V6_vtmpybus : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; -def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">; +def int_hexagon_V6_vtmpybus_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; -def int_hexagon_V6_vmaskedstoreq : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">; +def int_hexagon_V6_vd0 : +Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; -def int_hexagon_V6_vmaskedstorenq : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">; +def int_hexagon_V6_vd0_128B : +Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; -def int_hexagon_V6_vmaskedstorentq : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">; +def int_hexagon_V6_veqh_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">; -def int_hexagon_V6_vmaskedstorentnq : -Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">; +def int_hexagon_V6_veqh_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">; -def int_hexagon_V6_vmaskedstoreq_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">; +def int_hexagon_V6_vgtw_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">; -def int_hexagon_V6_vmaskedstorenq_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">; +def int_hexagon_V6_vgtw_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; -def int_hexagon_V6_vmaskedstorentq_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">; +def int_hexagon_V6_vdmpybus : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; -def int_hexagon_V6_vmaskedstorentnq_128B : -Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">; +def int_hexagon_V6_vdmpybus_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; -multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { - def NAME#_pci : Hexagon_NonGCC_Intrinsic< - [ElTy, llvm_ptr_ty], - [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], - [IntrArgMemOnly, NoCapture<3>]>; - def NAME#_pcr : Hexagon_NonGCC_Intrinsic< - [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], - [IntrArgMemOnly, NoCapture<2>]>; -} +def int_hexagon_V6_vgtub_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">; -defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; -defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; -defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; -defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; -defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; -defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; +def int_hexagon_V6_vgtub_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; -multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { - def NAME#_pci : Hexagon_NonGCC_Intrinsic< - [llvm_ptr_ty], - [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], - [IntrArgMemOnly, NoCapture<4>]>; - def NAME#_pcr : Hexagon_NonGCC_Intrinsic< - [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], - [IntrArgMemOnly, NoCapture<3>]>; -} +def int_hexagon_V6_vmpybus : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; -defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; -defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; -defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; -defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; -defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; +def int_hexagon_V6_vmpybus_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; -// The front-end emits the intrinsic call with only two arguments. The third -// argument from the builtin is already used by front-end to write to memory -// by generating a store. -class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> - : Hexagon_NonGCC_Intrinsic< - [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], - [IntrReadMem]>; +def int_hexagon_V6_vdmpyhb_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; -def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; -def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; -def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; -def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; -def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; -def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; +def int_hexagon_V6_vdmpyhb_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; -def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; -def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; -def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; -def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; -def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; +def int_hexagon_V6_vandvrt_acc : +Hexagon_v512i1_v512i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">; +def int_hexagon_V6_vandvrt_acc_128B : +Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; -/// -/// HexagonV62 intrinsics -/// +def int_hexagon_V6_vassign : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; -// -// Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix> -// tag : M6_vabsdiffb -class Hexagon_LLiLLiLLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vassign_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; -// -// Hexagon_LLii_Intrinsic<string GCCIntSuffix> -// tag : S6_vsplatrbp -class Hexagon_LLii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i64_ty], [llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddwnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">; -// -// Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlsrb -class Hexagon_V62_v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddwnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; -// -// Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlsrb_128B -class Hexagon_V62_v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vgtub_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">; -// -// Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vasrwuhrndsat -class Hexagon_V62_v512v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vgtub_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; -// -// Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vasrwuhrndsat_128B -class Hexagon_V62_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vdmpyhb_dv : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; -// -// Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vrounduwuh -class Hexagon_V62_v512v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vdmpyhb_dv_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; -// -// Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vrounduwuh_128B -class Hexagon_V62_v1024v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vunpackb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; -// -// Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix> -// tag : V6_vadduwsat_dv_128B -class Hexagon_V62_v2048v2048v2048_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vunpackb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; -// -// Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddhw_acc -class Hexagon_V62_v1024v1024v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vunpackh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; -// -// Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vaddhw_acc_128B -class Hexagon_V62_v2048v2048v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vunpackh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; -// -// Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyewuh_64 -class Hexagon_V62_v1024v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpahb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; -// -// Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyewuh_64_128B -class Hexagon_V62_v2048v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpahb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; -// -// Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpauhb_128B -class Hexagon_V62_v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddbnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">; -// -// Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpauhb_acc_128B -class Hexagon_V62_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddbnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; -// -// Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandnqrt -class Hexagon_V62_v512v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vlalignbi : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi">; -// -// Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandnqrt_128B -class Hexagon_V62_v1024v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vlalignbi_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B">; -// -// Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandnqrt_acc -class Hexagon_V62_v512v512v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vsatwh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; -// -// Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_vandnqrt_acc_128B -class Hexagon_V62_v1024v1024v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vsatwh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; -// -// Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvqv -class Hexagon_V62_v512v64iv512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vgtuh : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">; -// -// Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vandvqv_128B -class Hexagon_V62_v1024v128iv1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vgtuh_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">; -// -// Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_scalar2v2 -class Hexagon_V62_v64ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpyihb_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; -// -// Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix> -// tag : V6_pred_scalar2v2_128B -class Hexagon_V62_v128ii_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpyihb_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; -// -// Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix> -// tag : V6_shuffeqw -class Hexagon_V62_v64iv64iv64i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrmpybusv_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; -// -// Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix> -// tag : V6_shuffeqw_128B -class Hexagon_V62_v128iv128iv128i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrmpybusv_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; -// -// Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_lvsplath -class Hexagon_V62_v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrdelta : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; -// -// Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_lvsplath_128B -class Hexagon_V62_v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrdelta_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; -// -// Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvvb_oracci -class Hexagon_V62_v512v512v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vroundwh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; -// -// Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvvb_oracci_128B -class Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vroundwh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; -// -// Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvwhi -class Hexagon_V62_v1024v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddw_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; -// -// Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvwhi_128B -class Hexagon_V62_v2048v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vaddw_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; -// -// Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvwh_oracci -class Hexagon_V62_v1024v1024v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpyiwb_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; -// -// Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vlutvwh_oracci_128B -class Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpyiwb_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; -// Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix> -// tag: V6_vaddcarry -class Hexagon_v512v64iv512v512v64i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty, llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_vsubbq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">; -// Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix> -// tag: V6_vaddcarry_128B -class Hexagon_v1024v128iv1024v1024v128i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty, llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_vsubbq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">; +def int_hexagon_V6_veqh_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">; -// -// BUILTIN_INFO(HEXAGON.M6_vabsdiffb,DI_ftype_DIDI,2) -// tag : M6_vabsdiffb -def int_hexagon_M6_vabsdiffb : -Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffb">; +def int_hexagon_V6_veqh_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">; -// -// BUILTIN_INFO(HEXAGON.M6_vabsdiffub,DI_ftype_DIDI,2) -// tag : M6_vabsdiffub -def int_hexagon_M6_vabsdiffub : -Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_M6_vabsdiffub">; +def int_hexagon_V6_valignbi : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi">; -// -// BUILTIN_INFO(HEXAGON.S6_vtrunehb_ppp,DI_ftype_DIDI,2) -// tag : S6_vtrunehb_ppp -def int_hexagon_S6_vtrunehb_ppp : -Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; +def int_hexagon_V6_valignbi_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B">; -// -// BUILTIN_INFO(HEXAGON.S6_vtrunohb_ppp,DI_ftype_DIDI,2) -// tag : S6_vtrunohb_ppp -def int_hexagon_S6_vtrunohb_ppp : -Hexagon_LLiLLiLLi_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; +def int_hexagon_V6_vaddwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; -// -// BUILTIN_INFO(HEXAGON.S6_vsplatrbp,DI_ftype_SI,1) -// tag : S6_vsplatrbp -def int_hexagon_S6_vsplatrbp : -Hexagon_LLii_Intrinsic<"HEXAGON_S6_vsplatrbp">; +def int_hexagon_V6_vaddwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrb,VI_ftype_VISI,2) -// tag : V6_vlsrb -def int_hexagon_V6_vlsrb : -Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vlsrb">; +def int_hexagon_V6_veqw_and : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">; -// -// BUILTIN_INFO(HEXAGON.V6_vlsrb_128B,VI_ftype_VISI,2) -// tag : V6_vlsrb_128B -def int_hexagon_V6_vlsrb_128B : -Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vlsrb_128B">; +def int_hexagon_V6_veqw_and_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasrwuhrndsat -def int_hexagon_V6_vasrwuhrndsat : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; +def int_hexagon_V6_vabsdiffub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrwuhrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrwuhrndsat_128B -def int_hexagon_V6_vasrwuhrndsat_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; +def int_hexagon_V6_vabsdiffub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasruwuhrndsat -def int_hexagon_V6_vasruwuhrndsat : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; +def int_hexagon_V6_vshuffeb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruwuhrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasruwuhrndsat_128B -def int_hexagon_V6_vasruwuhrndsat_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; +def int_hexagon_V6_vshuffeb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhbsat,VI_ftype_VIVISI,3) -// tag : V6_vasrhbsat -def int_hexagon_V6_vasrhbsat : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrhbsat">; +def int_hexagon_V6_vabsdiffuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrhbsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrhbsat_128B -def int_hexagon_V6_vasrhbsat_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; +def int_hexagon_V6_vabsdiffuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrounduwuh,VI_ftype_VIVI,2) -// tag : V6_vrounduwuh -def int_hexagon_V6_vrounduwuh : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduwuh">; +def int_hexagon_V6_veqw_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vrounduwuh_128B,VI_ftype_VIVI,2) -// tag : V6_vrounduwuh_128B -def int_hexagon_V6_vrounduwuh_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; +def int_hexagon_V6_veqw_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrounduhub,VI_ftype_VIVI,2) -// tag : V6_vrounduhub -def int_hexagon_V6_vrounduhub : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vrounduhub">; +def int_hexagon_V6_vgth : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">; -// -// BUILTIN_INFO(HEXAGON.V6_vrounduhub_128B,VI_ftype_VIVI,2) -// tag : V6_vrounduhub_128B -def int_hexagon_V6_vrounduhub_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; +def int_hexagon_V6_vgth_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduwsat,VI_ftype_VIVI,2) -// tag : V6_vadduwsat -def int_hexagon_V6_vadduwsat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vadduwsat">; +def int_hexagon_V6_vgtuw_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduwsat_128B,VI_ftype_VIVI,2) -// tag : V6_vadduwsat_128B -def int_hexagon_V6_vadduwsat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; +def int_hexagon_V6_vgtuw_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv,VD_ftype_VDVD,2) -// tag : V6_vadduwsat_dv -def int_hexagon_V6_vadduwsat_dv : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; +def int_hexagon_V6_vgtb : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduwsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vadduwsat_dv_128B -def int_hexagon_V6_vadduwsat_dv_128B : -Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; +def int_hexagon_V6_vgtb_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuwsat,VI_ftype_VIVI,2) -// tag : V6_vsubuwsat -def int_hexagon_V6_vsubuwsat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubuwsat">; +def int_hexagon_V6_vgtw : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuwsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubuwsat_128B -def int_hexagon_V6_vsubuwsat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; +def int_hexagon_V6_vgtw_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsubuwsat_dv -def int_hexagon_V6_vsubuwsat_dv : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; +def int_hexagon_V6_vsubwq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubuwsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubuwsat_dv_128B -def int_hexagon_V6_vsubuwsat_dv_128B : -Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; +def int_hexagon_V6_vsubwq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbsat,VI_ftype_VIVI,2) -// tag : V6_vaddbsat -def int_hexagon_V6_vaddbsat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddbsat">; +def int_hexagon_V6_vnot : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbsat_128B,VI_ftype_VIVI,2) -// tag : V6_vaddbsat_128B -def int_hexagon_V6_vaddbsat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; +def int_hexagon_V6_vnot_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv,VD_ftype_VDVD,2) -// tag : V6_vaddbsat_dv -def int_hexagon_V6_vaddbsat_dv : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; +def int_hexagon_V6_vgtb_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddbsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vaddbsat_dv_128B -def int_hexagon_V6_vaddbsat_dv_128B : -Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; +def int_hexagon_V6_vgtb_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbsat,VI_ftype_VIVI,2) -// tag : V6_vsubbsat -def int_hexagon_V6_vsubbsat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubbsat">; +def int_hexagon_V6_vgtuw_or : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbsat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubbsat_128B -def int_hexagon_V6_vsubbsat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; +def int_hexagon_V6_vgtuw_or_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv,VD_ftype_VDVD,2) -// tag : V6_vsubbsat_dv -def int_hexagon_V6_vsubbsat_dv : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; +def int_hexagon_V6_vaddubsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubbsat_dv_128B,VD_ftype_VDVD,2) -// tag : V6_vsubbsat_dv_128B -def int_hexagon_V6_vsubbsat_dv_128B : -Hexagon_V62_v2048v2048v2048_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; +def int_hexagon_V6_vaddubsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddububb_sat,VI_ftype_VIVI,2) -// tag : V6_vaddububb_sat -def int_hexagon_V6_vaddububb_sat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddububb_sat">; +def int_hexagon_V6_vmaxw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddububb_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vaddububb_sat_128B -def int_hexagon_V6_vaddububb_sat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; +def int_hexagon_V6_vmaxw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubububb_sat,VI_ftype_VIVI,2) -// tag : V6_vsubububb_sat -def int_hexagon_V6_vsubububb_sat : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsubububb_sat">; +def int_hexagon_V6_vaslwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubububb_sat_128B,VI_ftype_VIVI,2) -// tag : V6_vsubububb_sat_128B -def int_hexagon_V6_vsubububb_sat_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; +def int_hexagon_V6_vaslwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhw_acc,VD_ftype_VDVIVI,3) -// tag : V6_vaddhw_acc -def int_hexagon_V6_vaddhw_acc : -Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddhw_acc">; +def int_hexagon_V6_vabsw_sat : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddhw_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vaddhw_acc_128B -def int_hexagon_V6_vaddhw_acc_128B : -Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; +def int_hexagon_V6_vabsw_sat_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhw_acc,VD_ftype_VDVIVI,3) -// tag : V6_vadduhw_acc -def int_hexagon_V6_vadduhw_acc : -Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vadduhw_acc">; +def int_hexagon_V6_vsubwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vadduhw_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vadduhw_acc_128B -def int_hexagon_V6_vadduhw_acc_128B : -Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; +def int_hexagon_V6_vsubwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubh_acc,VD_ftype_VDVIVI,3) -// tag : V6_vaddubh_acc -def int_hexagon_V6_vaddubh_acc : -Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vaddubh_acc">; +def int_hexagon_V6_vroundhub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddubh_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vaddubh_acc_128B -def int_hexagon_V6_vaddubh_acc_128B : -Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; +def int_hexagon_V6_vroundhub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64,VD_ftype_VIVI,2) -// tag : V6_vmpyewuh_64 -def int_hexagon_V6_vmpyewuh_64 : -Hexagon_V62_v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; +def int_hexagon_V6_vdmpyhisat_acc : +Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyewuh_64_128B,VD_ftype_VIVI,2) -// tag : V6_vmpyewuh_64_128B -def int_hexagon_V6_vmpyewuh_64_128B : -Hexagon_V62_v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; +def int_hexagon_V6_vdmpyhisat_acc_128B : +Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc,VD_ftype_VDVIVI,3) -// tag : V6_vmpyowh_64_acc -def int_hexagon_V6_vmpyowh_64_acc : -Hexagon_V62_v1024v1024v512v512_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; +def int_hexagon_V6_vmpabus : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyowh_64_acc_128B,VD_ftype_VDVIVI,3) -// tag : V6_vmpyowh_64_acc_128B -def int_hexagon_V6_vmpyowh_64_acc_128B : -Hexagon_V62_v2048v2048v1024v1024_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; +def int_hexagon_V6_vmpabus_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhb,VD_ftype_VDSI,2) -// tag : V6_vmpauhb -def int_hexagon_V6_vmpauhb : -Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb">; +def int_hexagon_V6_vassignp : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhb_128B,VD_ftype_VDSI,2) -// tag : V6_vmpauhb_128B -def int_hexagon_V6_vmpauhb_128B : -Hexagon_V62_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; +def int_hexagon_V6_vassignp_128B : +Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc,VD_ftype_VDVDSI,3) -// tag : V6_vmpauhb_acc -def int_hexagon_V6_vmpauhb_acc : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; +def int_hexagon_V6_veqb : +Hexagon_v512i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhb_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vmpauhb_acc_128B -def int_hexagon_V6_vmpauhb_acc_128B : -Hexagon_V62_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; +def int_hexagon_V6_veqb_128B : +Hexagon_v1024i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwub,VI_ftype_VISI,2) -// tag : V6_vmpyiwub -def int_hexagon_V6_vmpyiwub : -Hexagon_V62_v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub">; +def int_hexagon_V6_vsububh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwub_128B,VI_ftype_VISI,2) -// tag : V6_vmpyiwub_128B -def int_hexagon_V6_vmpyiwub_128B : -Hexagon_V62_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; +def int_hexagon_V6_vsububh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwub_acc -def int_hexagon_V6_vmpyiwub_acc : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; +def int_hexagon_V6_lvsplatw : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyiwub_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vmpyiwub_acc_128B -def int_hexagon_V6_vmpyiwub_acc_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; +def int_hexagon_V6_lvsplatw_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vandnqrt,VI_ftype_QVSI,2) -// tag : V6_vandnqrt -def int_hexagon_V6_vandnqrt : -Hexagon_V62_v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt">; +def int_hexagon_V6_vaddhnq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">; -// -// BUILTIN_INFO(HEXAGON.V6_vandnqrt_128B,VI_ftype_QVSI,2) -// tag : V6_vandnqrt_128B -def int_hexagon_V6_vandnqrt_128B : -Hexagon_V62_v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; +def int_hexagon_V6_vaddhnq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc,VI_ftype_VIQVSI,3) -// tag : V6_vandnqrt_acc -def int_hexagon_V6_vandnqrt_acc : -Hexagon_V62_v512v512v64ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; +def int_hexagon_V6_vdmpyhsusat : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; -// -// BUILTIN_INFO(HEXAGON.V6_vandnqrt_acc_128B,VI_ftype_VIQVSI,3) -// tag : V6_vandnqrt_acc_128B -def int_hexagon_V6_vandnqrt_acc_128B : -Hexagon_V62_v1024v1024v128ii_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; +def int_hexagon_V6_vdmpyhsusat_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvqv,VI_ftype_QVVI,2) -// tag : V6_vandvqv -def int_hexagon_V6_vandvqv : -Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvqv">; +def int_hexagon_V6_pred_not : +Hexagon_v512i1_v512i1_Intrinsic<"HEXAGON_V6_pred_not">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvqv_128B,VI_ftype_QVVI,2) -// tag : V6_vandvqv_128B -def int_hexagon_V6_vandvqv_128B : -Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvqv_128B">; +def int_hexagon_V6_pred_not_128B : +Hexagon_v1024i1_v1024i1_Intrinsic<"HEXAGON_V6_pred_not_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvnqv,VI_ftype_QVVI,2) -// tag : V6_vandvnqv -def int_hexagon_V6_vandvnqv : -Hexagon_V62_v512v64iv512_Intrinsic<"HEXAGON_V6_vandvnqv">; +def int_hexagon_V6_vlutvwh_oracc : +Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; -// -// BUILTIN_INFO(HEXAGON.V6_vandvnqv_128B,VI_ftype_QVVI,2) -// tag : V6_vandvnqv_128B -def int_hexagon_V6_vandvnqv_128B : -Hexagon_V62_v1024v128iv1024_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; +def int_hexagon_V6_vlutvwh_oracc_128B : +Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2,QV_ftype_SI,1) -// tag : V6_pred_scalar2v2 -def int_hexagon_V6_pred_scalar2v2 : -Hexagon_V62_v64ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; +def int_hexagon_V6_vmpyiewh_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_pred_scalar2v2_128B,QV_ftype_SI,1) -// tag : V6_pred_scalar2v2_128B -def int_hexagon_V6_pred_scalar2v2_128B : -Hexagon_V62_v128ii_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; +def int_hexagon_V6_vmpyiewh_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_shuffeqw,QV_ftype_QVQV,2) -// tag : V6_shuffeqw -def int_hexagon_V6_shuffeqw : -Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqw">; +def int_hexagon_V6_vdealvdd : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; -// -// BUILTIN_INFO(HEXAGON.V6_shuffeqw_128B,QV_ftype_QVQV,2) -// tag : V6_shuffeqw_128B -def int_hexagon_V6_shuffeqw_128B : -Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; +def int_hexagon_V6_vdealvdd_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_shuffeqh,QV_ftype_QVQV,2) -// tag : V6_shuffeqh -def int_hexagon_V6_shuffeqh : -Hexagon_V62_v64iv64iv64i_Intrinsic<"HEXAGON_V6_shuffeqh">; +def int_hexagon_V6_vavgw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; -// -// BUILTIN_INFO(HEXAGON.V6_shuffeqh_128B,QV_ftype_QVQV,2) -// tag : V6_shuffeqh_128B -def int_hexagon_V6_shuffeqh_128B : -Hexagon_V62_v128iv128iv128i_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; +def int_hexagon_V6_vavgw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxb,VI_ftype_VIVI,2) -// tag : V6_vmaxb -def int_hexagon_V6_vmaxb : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vmaxb">; +def int_hexagon_V6_vdmpyhsusat_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmaxb_128B,VI_ftype_VIVI,2) -// tag : V6_vmaxb_128B -def int_hexagon_V6_vmaxb_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vmaxb_128B">; +def int_hexagon_V6_vdmpyhsusat_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vminb,VI_ftype_VIVI,2) -// tag : V6_vminb -def int_hexagon_V6_vminb : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vminb">; +def int_hexagon_V6_vgtw_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">; -// -// BUILTIN_INFO(HEXAGON.V6_vminb_128B,VI_ftype_VIVI,2) -// tag : V6_vminb_128B -def int_hexagon_V6_vminb_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vminb_128B">; +def int_hexagon_V6_vgtw_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsatuwuh,VI_ftype_VIVI,2) -// tag : V6_vsatuwuh -def int_hexagon_V6_vsatuwuh : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vsatuwuh">; +def int_hexagon_V6_vtmpyhb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vsatuwuh_128B,VI_ftype_VIVI,2) -// tag : V6_vsatuwuh_128B -def int_hexagon_V6_vsatuwuh_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; +def int_hexagon_V6_vtmpyhb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplath,VI_ftype_SI,1) -// tag : V6_lvsplath -def int_hexagon_V6_lvsplath : -Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplath">; +def int_hexagon_V6_vaddhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplath_128B,VI_ftype_SI,1) -// tag : V6_lvsplath_128B -def int_hexagon_V6_lvsplath_128B : -Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplath_128B">; +def int_hexagon_V6_vaddhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplatb,VI_ftype_SI,1) -// tag : V6_lvsplatb -def int_hexagon_V6_lvsplatb : -Hexagon_V62_v512i_Intrinsic<"HEXAGON_V6_lvsplatb">; +def int_hexagon_V6_vaddhq : +Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">; -// -// BUILTIN_INFO(HEXAGON.V6_lvsplatb_128B,VI_ftype_SI,1) -// tag : V6_lvsplatb_128B -def int_hexagon_V6_lvsplatb_128B : -Hexagon_V62_v1024i_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; +def int_hexagon_V6_vaddhq_128B : +Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddclbw,VI_ftype_VIVI,2) -// tag : V6_vaddclbw -def int_hexagon_V6_vaddclbw : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbw">; +def int_hexagon_V6_vrmpyubv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddclbw_128B,VI_ftype_VIVI,2) -// tag : V6_vaddclbw_128B -def int_hexagon_V6_vaddclbw_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; +def int_hexagon_V6_vrmpyubv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; + +def int_hexagon_V6_vsubh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; + +def int_hexagon_V6_vsubh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; + +def int_hexagon_V6_vrmpyubi : +Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi">; + +def int_hexagon_V6_vrmpyubi_128B : +Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B">; + +def int_hexagon_V6_vminw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; + +def int_hexagon_V6_vminw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; + +def int_hexagon_V6_vmpyubv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; + +def int_hexagon_V6_vmpyubv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; + +def int_hexagon_V6_pred_xor : +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_pred_xor">; + +def int_hexagon_V6_pred_xor_128B : +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">; + +def int_hexagon_V6_veqb_xor : +Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">; + +def int_hexagon_V6_veqb_xor_128B : +Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; + +def int_hexagon_V6_vmpyiewuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; + +def int_hexagon_V6_vmpyiewuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; + +def int_hexagon_V6_vmpybusv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; + +def int_hexagon_V6_vmpybusv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; + +def int_hexagon_V6_vavguhrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; + +def int_hexagon_V6_vavguhrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; + +def int_hexagon_V6_vmpyowh_rnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; + +def int_hexagon_V6_vmpyowh_rnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; + +def int_hexagon_V6_vsubwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; + +def int_hexagon_V6_vsubwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; + +def int_hexagon_V6_vsubuhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; + +def int_hexagon_V6_vsubuhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; + +def int_hexagon_V6_vrmpybusi_acc : +Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc">; + +def int_hexagon_V6_vrmpybusi_acc_128B : +Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B">; + +def int_hexagon_V6_vasrw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; + +def int_hexagon_V6_vasrw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; + +def int_hexagon_V6_vasrh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; + +def int_hexagon_V6_vasrh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; + +def int_hexagon_V6_vmpyuhv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; + +def int_hexagon_V6_vmpyuhv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; + +def int_hexagon_V6_vasrhbrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; + +def int_hexagon_V6_vasrhbrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; + +def int_hexagon_V6_vsubuhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; + +def int_hexagon_V6_vsubuhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; + +def int_hexagon_V6_vabsdiffw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; + +def int_hexagon_V6_vabsdiffw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; + +// V62 HVX Instructions. + +def int_hexagon_V6_vandnqrt_acc : +Hexagon_v16i32_v16i32v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; + +def int_hexagon_V6_vandnqrt_acc_128B : +Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddclbh,VI_ftype_VIVI,2) -// tag : V6_vaddclbh def int_hexagon_V6_vaddclbh : -Hexagon_V62_v512v512v512_Intrinsic<"HEXAGON_V6_vaddclbh">; +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddclbh_128B,VI_ftype_VIVI,2) -// tag : V6_vaddclbh_128B def int_hexagon_V6_vaddclbh_128B : -Hexagon_V62_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvbi,VI_ftype_VIVISI,3) -// tag : V6_vlutvvbi -def int_hexagon_V6_vlutvvbi : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvbi">; +def int_hexagon_V6_vmpyowh_64_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvbi_128B,VI_ftype_VIVISI,3) -// tag : V6_vlutvvbi_128B -def int_hexagon_V6_vlutvvbi_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">; +def int_hexagon_V6_vmpyowh_64_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci,VI_ftype_VIVIVISI,4) -// tag : V6_vlutvvb_oracci -def int_hexagon_V6_vlutvvb_oracci : -Hexagon_V62_v512v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">; +def int_hexagon_V6_vmpyewuh_64 : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_oracci_128B,VI_ftype_VIVIVISI,4) -// tag : V6_vlutvvb_oracci_128B -def int_hexagon_V6_vlutvvb_oracci_128B : -Hexagon_V62_v1024v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">; +def int_hexagon_V6_vmpyewuh_64_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; + +def int_hexagon_V6_vsatuwuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; + +def int_hexagon_V6_vsatuwuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; + +def int_hexagon_V6_shuffeqh : +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqh">; + +def int_hexagon_V6_shuffeqh_128B : +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; + +def int_hexagon_V6_shuffeqw : +Hexagon_v512i1_v512i1v512i1_Intrinsic<"HEXAGON_V6_shuffeqw">; + +def int_hexagon_V6_shuffeqw_128B : +Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; + +def int_hexagon_V6_ldcnpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0">; + +def int_hexagon_V6_ldcnpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnpnt0_128B">; + +def int_hexagon_V6_vsubcarry : +Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic; + +def int_hexagon_V6_vsubcarry_128B : +Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B; + +def int_hexagon_V6_vasrhbsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; + +def int_hexagon_V6_vasrhbsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; + +def int_hexagon_V6_vminb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; + +def int_hexagon_V6_vminb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; + +def int_hexagon_V6_vmpauhb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; + +def int_hexagon_V6_vmpauhb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; + +def int_hexagon_V6_vaddhw_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; + +def int_hexagon_V6_vaddhw_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; + +def int_hexagon_V6_vlsrb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; + +def int_hexagon_V6_vlsrb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwhi,VD_ftype_VIVISI,3) -// tag : V6_vlutvwhi def int_hexagon_V6_vlutvwhi : -Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwhi">; +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwhi_128B,VD_ftype_VIVISI,3) -// tag : V6_vlutvwhi_128B def int_hexagon_V6_vlutvwhi_128B : -Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">; +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci,VD_ftype_VDVIVISI,4) -// tag : V6_vlutvwh_oracci -def int_hexagon_V6_vlutvwh_oracci : -Hexagon_V62_v1024v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">; +def int_hexagon_V6_vaddububb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_oracci_128B,VD_ftype_VDVIVISI,4) -// tag : V6_vlutvwh_oracci_128B -def int_hexagon_V6_vlutvwh_oracci_128B : -Hexagon_V62_v2048v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">; +def int_hexagon_V6_vaddububb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm,VI_ftype_VIVISI,3) -// tag : V6_vlutvvb_nm -def int_hexagon_V6_vlutvvb_nm : -Hexagon_V62_v512v512v512i_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; +def int_hexagon_V6_vsubbsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvvb_nm_128B,VI_ftype_VIVISI,3) -// tag : V6_vlutvvb_nm_128B -def int_hexagon_V6_vlutvvb_nm_128B : -Hexagon_V62_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; +def int_hexagon_V6_vsubbsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm,VD_ftype_VIVISI,3) -// tag : V6_vlutvwh_nm -def int_hexagon_V6_vlutvwh_nm : -Hexagon_V62_v1024v512v512i_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; +def int_hexagon_V6_ldtp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0">; -// -// BUILTIN_INFO(HEXAGON.V6_vlutvwh_nm_128B,VD_ftype_VIVISI,3) -// tag : V6_vlutvwh_nm_128B -def int_hexagon_V6_vlutvwh_nm_128B : -Hexagon_V62_v2048v1024v1024i_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; +def int_hexagon_V6_ldtp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtp0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddcarry,VI_ftype_VIVIQV,3) -// tag: V6_vaddcarry -def int_hexagon_V6_vaddcarry : -Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vaddcarry">; +def int_hexagon_V6_vlutvvb_oracci : +Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci">; -// -// BUILTIN_INFO(HEXAGON.V6_vaddcarry_128B,VI_ftype_VIVIQV,3) -// tag: V6_vaddcarry_128B -def int_hexagon_V6_vaddcarry_128B : -Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vaddcarry_128B">; +def int_hexagon_V6_vlutvvb_oracci_128B : +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubcarry,VI_ftype_VIVIQV,3) -// tag: V6_vsubcarry -def int_hexagon_V6_vsubcarry : -Hexagon_v512v64iv512v512v64i_Intrinsic<"HEXAGON_v6_vsubcarry">; +def int_hexagon_V6_vsubuwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vsubcarry_128B,VI_ftype_VIVIQV,3) -// tag: V6_vsubcarry_128B -def int_hexagon_V6_vsubcarry_128B : -Hexagon_v1024v128iv1024v1024v128i_Intrinsic<"HEXAGON_v6_vsubcarry_128B">; +def int_hexagon_V6_vsubuwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; +def int_hexagon_V6_ldpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0">; -/// -/// HexagonV65 intrinsics -/// +def int_hexagon_V6_ldpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldpnt0_128B">; -// -// Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix> -// tag : A6_vcmpbeq_notany -class Hexagon_V65_iLLiLLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vandvnqv : +Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">; -// -// Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyub_rtt -class Hexagon_V65_v1024v512LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vandvnqv_128B : +Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; -// -// Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyub_rtt_128B -class Hexagon_V65_v2048v1024LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_lvsplatb : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; -// -// Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyub_rtt_acc -class Hexagon_V65_v1024v1024v512LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_lvsplatb_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; -// -// Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vrmpyub_rtt_acc_128B -class Hexagon_V65_v2048v2048v1024LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_lvsplath : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; -// -// Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vasruwuhsat -class Hexagon_V65_v512v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_lvsplath_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; -// -// Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vasruwuhsat_128B -class Hexagon_V65_v1024v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldtpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0">; -// -// Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vavguw -class Hexagon_V65_v512v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldtpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtpnt0_128B">; -// -// Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vavguw_128B -class Hexagon_V65_v1024v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vlutvwh_nm : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; -// -// Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix> -// tag : V6_vabsb -class Hexagon_V65_v512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vlutvwh_nm_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; -// -// Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix> -// tag : V6_vabsb_128B -class Hexagon_V65_v1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldnpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0">; -// -// Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpabuu -class Hexagon_V65_v1024v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldnpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnpnt0_128B">; -// -// Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpabuu_128B -class Hexagon_V65_v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpauhb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; -// -// Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpabuu_acc_128B -class Hexagon_V65_v2048v2048v2048i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_vmpauhb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; -// -// Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyh_acc -class Hexagon_V65_v1024v1024v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldtnp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0">; -// -// Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyh_acc_128B -class Hexagon_V65_v2048v2048v1024i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldtnp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnp0_128B">; -// -// Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpahhsat -class Hexagon_V65_v512v512v512LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrounduhub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; -// -// Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpahhsat_128B -class Hexagon_V65_v1024v1024v1024LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vrounduhub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; -// -// Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vlut4 -class Hexagon_V65_v512v512LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vadduhw_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; -// -// Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix> -// tag : V6_vlut4_128B -class Hexagon_V65_v1024v1024LLi_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], - [IntrNoMem]>; +def int_hexagon_V6_vadduhw_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; -// -// Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix> -// tag : V6_vmpyuhe -class Hexagon_V65_v512v512i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldcp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0">; -// -// Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix> -// tag : V6_vprefixqb -class Hexagon_V65_v512v64i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v16i32_ty], [llvm_v512i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_ldcp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcp0_128B">; -// -// Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix> -// tag : V6_vprefixqb_128B -class Hexagon_V65_v1024v128i_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v32i32_ty], [llvm_v1024i1_ty], - [IntrNoMem]>; +def int_hexagon_V6_vadduwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; -// -// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany,QI_ftype_DIDI,2) -// tag : A6_vcmpbeq_notany -def int_hexagon_A6_vcmpbeq_notany : -Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; +def int_hexagon_V6_vadduwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; -// -// BUILTIN_INFO(HEXAGON.A6_vcmpbeq_notany_128B,QI_ftype_DIDI,2) -// tag : A6_vcmpbeq_notany_128B -def int_hexagon_A6_vcmpbeq_notany_128B : -Hexagon_V65_iLLiLLi_Intrinsic<"HEXAGON_A6_vcmpbeq_notany_128B">; +def int_hexagon_V6_ldtnpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt,VD_ftype_VIDI,2) -// tag : V6_vrmpyub_rtt -def int_hexagon_V6_vrmpyub_rtt : -Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; +def int_hexagon_V6_ldtnpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldtnpnt0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_128B,VD_ftype_VIDI,2) -// tag : V6_vrmpyub_rtt_128B -def int_hexagon_V6_vrmpyub_rtt_128B : -Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; +def int_hexagon_V6_vaddbsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc,VD_ftype_VDVIDI,3) -// tag : V6_vrmpyub_rtt_acc -def int_hexagon_V6_vrmpyub_rtt_acc : -Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; +def int_hexagon_V6_vaddbsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpyub_rtt_acc_128B,VD_ftype_VDVIDI,3) -// tag : V6_vrmpyub_rtt_acc_128B -def int_hexagon_V6_vrmpyub_rtt_acc_128B : -Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; +def int_hexagon_V6_vandnqrt : +Hexagon_v16i32_v512i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt,VD_ftype_VIDI,2) -// tag : V6_vrmpybub_rtt -def int_hexagon_V6_vrmpybub_rtt : -Hexagon_V65_v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; +def int_hexagon_V6_vandnqrt_128B : +Hexagon_v32i32_v1024i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_128B,VD_ftype_VIDI,2) -// tag : V6_vrmpybub_rtt_128B -def int_hexagon_V6_vrmpybub_rtt_128B : -Hexagon_V65_v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; +def int_hexagon_V6_vmpyiwub_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc,VD_ftype_VDVIDI,3) -// tag : V6_vrmpybub_rtt_acc -def int_hexagon_V6_vrmpybub_rtt_acc : -Hexagon_V65_v1024v1024v512LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; +def int_hexagon_V6_vmpyiwub_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vrmpybub_rtt_acc_128B,VD_ftype_VDVIDI,3) -// tag : V6_vrmpybub_rtt_acc_128B -def int_hexagon_V6_vrmpybub_rtt_acc_128B : -Hexagon_V65_v2048v2048v1024LLi_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; +def int_hexagon_V6_vmaxb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat,VI_ftype_VIVISI,3) -// tag : V6_vasruwuhsat -def int_hexagon_V6_vasruwuhsat : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruwuhsat">; +def int_hexagon_V6_vmaxb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruwuhsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasruwuhsat_128B -def int_hexagon_V6_vasruwuhsat_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; +def int_hexagon_V6_vandvqv : +Hexagon_v16i32_v512i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruhubsat,VI_ftype_VIVISI,3) -// tag : V6_vasruhubsat -def int_hexagon_V6_vasruhubsat : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubsat">; +def int_hexagon_V6_vandvqv_128B : +Hexagon_v32i32_v1024i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasruhubsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasruhubsat_128B -def int_hexagon_V6_vasruhubsat_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; +def int_hexagon_V6_vaddcarry : +Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic; -// -// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat,VI_ftype_VIVISI,3) -// tag : V6_vasruhubrndsat -def int_hexagon_V6_vasruhubrndsat : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; +def int_hexagon_V6_vaddcarry_128B : +Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B; -// -// BUILTIN_INFO(HEXAGON.V6_vasruhubrndsat_128B,VI_ftype_VIVISI,3) -// tag : V6_vasruhubrndsat_128B -def int_hexagon_V6_vasruhubrndsat_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; +def int_hexagon_V6_vasrwuhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslh_acc,VI_ftype_VIVISI,3) -// tag : V6_vaslh_acc -def int_hexagon_V6_vaslh_acc : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vaslh_acc">; +def int_hexagon_V6_vasrwuhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vaslh_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vaslh_acc_128B -def int_hexagon_V6_vaslh_acc_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; +def int_hexagon_V6_vlutvvbi : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrh_acc,VI_ftype_VIVISI,3) -// tag : V6_vasrh_acc -def int_hexagon_V6_vasrh_acc : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vasrh_acc">; +def int_hexagon_V6_vlutvvbi_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vasrh_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vasrh_acc_128B -def int_hexagon_V6_vasrh_acc_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; +def int_hexagon_V6_vsubuwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguw,VI_ftype_VIVI,2) -// tag : V6_vavguw -def int_hexagon_V6_vavguw : -Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguw">; +def int_hexagon_V6_vsubuwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguw_128B,VI_ftype_VIVI,2) -// tag : V6_vavguw_128B -def int_hexagon_V6_vavguw_128B : -Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguw_128B">; +def int_hexagon_V6_vaddbsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguwrnd,VI_ftype_VIVI,2) -// tag : V6_vavguwrnd -def int_hexagon_V6_vavguwrnd : -Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavguwrnd">; +def int_hexagon_V6_vaddbsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vavguwrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavguwrnd_128B -def int_hexagon_V6_vavguwrnd_128B : -Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; +def int_hexagon_V6_ldnp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgb,VI_ftype_VIVI,2) -// tag : V6_vavgb -def int_hexagon_V6_vavgb : -Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgb">; +def int_hexagon_V6_ldnp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldnp0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgb_128B,VI_ftype_VIVI,2) -// tag : V6_vavgb_128B -def int_hexagon_V6_vavgb_128B : -Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgb_128B">; +def int_hexagon_V6_vasruwuhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgbrnd,VI_ftype_VIVI,2) -// tag : V6_vavgbrnd -def int_hexagon_V6_vavgbrnd : -Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vavgbrnd">; +def int_hexagon_V6_vasruwuhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vavgbrnd_128B,VI_ftype_VIVI,2) -// tag : V6_vavgbrnd_128B -def int_hexagon_V6_vavgbrnd_128B : -Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; +def int_hexagon_V6_vrounduwuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgb,VI_ftype_VIVI,2) -// tag : V6_vnavgb -def int_hexagon_V6_vnavgb : -Hexagon_V65_v512v512v512_Intrinsic<"HEXAGON_V6_vnavgb">; +def int_hexagon_V6_vrounduwuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vnavgb_128B,VI_ftype_VIVI,2) -// tag : V6_vnavgb_128B -def int_hexagon_V6_vnavgb_128B : -Hexagon_V65_v1024v1024v1024_Intrinsic<"HEXAGON_V6_vnavgb_128B">; +def int_hexagon_V6_vlutvvb_nm : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsb,VI_ftype_VI,1) -// tag : V6_vabsb -def int_hexagon_V6_vabsb : -Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb">; +def int_hexagon_V6_vlutvvb_nm_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsb_128B,VI_ftype_VI,1) -// tag : V6_vabsb_128B -def int_hexagon_V6_vabsb_128B : -Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_128B">; +def int_hexagon_V6_pred_scalar2v2 : +Hexagon_v512i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsb_sat,VI_ftype_VI,1) -// tag : V6_vabsb_sat -def int_hexagon_V6_vabsb_sat : -Hexagon_V65_v512v512_Intrinsic<"HEXAGON_V6_vabsb_sat">; +def int_hexagon_V6_pred_scalar2v2_128B : +Hexagon_v1024i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vabsb_sat_128B,VI_ftype_VI,1) -// tag : V6_vabsb_sat_128B -def int_hexagon_V6_vabsb_sat_128B : -Hexagon_V65_v1024v1024_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; +def int_hexagon_V6_ldp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuu,VD_ftype_VDSI,2) -// tag : V6_vmpabuu -def int_hexagon_V6_vmpabuu : -Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu">; +def int_hexagon_V6_ldp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldp0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuu_128B,VD_ftype_VDSI,2) -// tag : V6_vmpabuu_128B -def int_hexagon_V6_vmpabuu_128B : -Hexagon_V65_v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; +def int_hexagon_V6_vaddubh_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc,VD_ftype_VDVDSI,3) -// tag : V6_vmpabuu_acc -def int_hexagon_V6_vmpabuu_acc : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; +def int_hexagon_V6_vaddubh_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpabuu_acc_128B,VD_ftype_VDVDSI,3) -// tag : V6_vmpabuu_acc_128B -def int_hexagon_V6_vmpabuu_acc_128B : -Hexagon_V65_v2048v2048v2048i_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; +def int_hexagon_V6_vaddclbw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc,VD_ftype_VDVISI,3) -// tag : V6_vmpyh_acc -def int_hexagon_V6_vmpyh_acc : -Hexagon_V65_v1024v1024v512i_Intrinsic<"HEXAGON_V6_vmpyh_acc">; +def int_hexagon_V6_vaddclbw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyh_acc_128B,VD_ftype_VDVISI,3) -// tag : V6_vmpyh_acc_128B -def int_hexagon_V6_vmpyh_acc_128B : -Hexagon_V65_v2048v2048v1024i_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; +def int_hexagon_V6_ldcpnt0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahhsat,VI_ftype_VIVIDI,3) -// tag : V6_vmpahhsat -def int_hexagon_V6_vmpahhsat : -Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpahhsat">; +def int_hexagon_V6_ldcpnt0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcpnt0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpahhsat_128B,VI_ftype_VIVIDI,3) -// tag : V6_vmpahhsat_128B -def int_hexagon_V6_vmpahhsat_128B : -Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; +def int_hexagon_V6_vadduwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat,VI_ftype_VIVIDI,3) -// tag : V6_vmpauhuhsat -def int_hexagon_V6_vmpauhuhsat : -Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; +def int_hexagon_V6_vadduwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpauhuhsat_128B,VI_ftype_VIVIDI,3) -// tag : V6_vmpauhuhsat_128B -def int_hexagon_V6_vmpauhuhsat_128B : -Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; +def int_hexagon_V6_vmpyiwub : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat,VI_ftype_VIVIDI,3) -// tag : V6_vmpsuhuhsat -def int_hexagon_V6_vmpsuhuhsat : -Hexagon_V65_v512v512v512LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; +def int_hexagon_V6_vmpyiwub_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpsuhuhsat_128B,VI_ftype_VIVIDI,3) -// tag : V6_vmpsuhuhsat_128B -def int_hexagon_V6_vmpsuhuhsat_128B : -Hexagon_V65_v1024v1024v1024LLi_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; +def int_hexagon_V6_vsubububb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; -// -// BUILTIN_INFO(HEXAGON.V6_vlut4,VI_ftype_VIDI,2) -// tag : V6_vlut4 -def int_hexagon_V6_vlut4 : -Hexagon_V65_v512v512LLi_Intrinsic<"HEXAGON_V6_vlut4">; +def int_hexagon_V6_vsubububb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vlut4_128B,VI_ftype_VIDI,2) -// tag : V6_vlut4_128B -def int_hexagon_V6_vlut4_128B : -Hexagon_V65_v1024v1024LLi_Intrinsic<"HEXAGON_V6_vlut4_128B">; +def int_hexagon_V6_ldcnp0 : +Hexagon_v16i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhe,VI_ftype_VISI,2) -// tag : V6_vmpyuhe -def int_hexagon_V6_vmpyuhe : -Hexagon_V65_v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe">; +def int_hexagon_V6_ldcnp0_128B : +Hexagon_v32i32_i32i32_Intrinsic<"HEXAGON_V6_ldcnp0_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_128B,VI_ftype_VISI,2) -// tag : V6_vmpyuhe_128B -def int_hexagon_V6_vmpyuhe_128B : -Hexagon_V65_v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; +def int_hexagon_V6_vlutvwh_oracci : +Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc,VI_ftype_VIVISI,3) -// tag : V6_vmpyuhe_acc -def int_hexagon_V6_vmpyuhe_acc : -Hexagon_V65_v512v512v512i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; +def int_hexagon_V6_vlutvwh_oracci_128B : +Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vmpyuhe_acc_128B,VI_ftype_VIVISI,3) -// tag : V6_vmpyuhe_acc_128B -def int_hexagon_V6_vmpyuhe_acc_128B : -Hexagon_V65_v1024v1024v1024i_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; +def int_hexagon_V6_vsubbsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqb,VI_ftype_QV,1) -// tag : V6_vprefixqb -def int_hexagon_V6_vprefixqb : -Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqb">; +def int_hexagon_V6_vsubbsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqb_128B,VI_ftype_QV,1) -// tag : V6_vprefixqb_128B -def int_hexagon_V6_vprefixqb_128B : -Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; +// V65 HVX Instructions. -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqh,VI_ftype_QV,1) -// tag : V6_vprefixqh -def int_hexagon_V6_vprefixqh : -Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqh">; +def int_hexagon_V6_vasruhubrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqh_128B,VI_ftype_QV,1) -// tag : V6_vprefixqh_128B -def int_hexagon_V6_vprefixqh_128B : -Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; +def int_hexagon_V6_vasruhubrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqw,VI_ftype_QV,1) -// tag : V6_vprefixqw -def int_hexagon_V6_vprefixqw : -Hexagon_V65_v512v64i_Intrinsic<"HEXAGON_V6_vprefixqw">; +def int_hexagon_V6_vrmpybub_rtt : +Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; -// -// BUILTIN_INFO(HEXAGON.V6_vprefixqw_128B,VI_ftype_QV,1) -// tag : V6_vprefixqw_128B -def int_hexagon_V6_vprefixqw_128B : -Hexagon_V65_v1024v128i_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; +def int_hexagon_V6_vrmpybub_rtt_128B : +Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; +def int_hexagon_V6_vmpahhsat : +Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; -// The scatter/gather ones below will not be generated from iset.py. Make sure -// you don't overwrite these. -class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, - llvm_v16i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vmpahhsat_128B : +Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; -class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, - llvm_v32i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vavguwrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; -class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty, - llvm_v64i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vavguwrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; -class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v16i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vnavgb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; -class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v32i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vnavgb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; -class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v32i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vasrh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; -class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v64i32_ty], - [IntrArgMemOnly]>; +def int_hexagon_V6_vasrh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; -def int_hexagon_V6_vgathermw : -Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">; +def int_hexagon_V6_vmpauhuhsat : +Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; -def int_hexagon_V6_vgathermw_128B : -Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">; +def int_hexagon_V6_vmpauhuhsat_128B : +Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; -def int_hexagon_V6_vgathermh : -Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">; +def int_hexagon_V6_vmpyh_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; -def int_hexagon_V6_vgathermh_128B : -Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">; +def int_hexagon_V6_vmpyh_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; -def int_hexagon_V6_vgathermhw : -Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">; +def int_hexagon_V6_vrmpybub_rtt_acc : +Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; -def int_hexagon_V6_vgathermhw_128B : -Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">; +def int_hexagon_V6_vrmpybub_rtt_acc_128B : +Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; -def int_hexagon_V6_vgathermwq : -Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">; +def int_hexagon_V6_vavgb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; -def int_hexagon_V6_vgathermwq_128B : -Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">; +def int_hexagon_V6_vavgb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; -def int_hexagon_V6_vgathermhq : -Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">; +def int_hexagon_V6_vaslh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; -def int_hexagon_V6_vgathermhq_128B : -Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">; +def int_hexagon_V6_vaslh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; -def int_hexagon_V6_vgathermhwq : -Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">; +def int_hexagon_V6_vavguw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; -def int_hexagon_V6_vgathermhwq_128B : -Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">; +def int_hexagon_V6_vavguw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; -class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_i32_ty,llvm_i32_ty, - llvm_v16i32_ty,llvm_v16i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vlut4 : +Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; -class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_i32_ty,llvm_i32_ty, - llvm_v32i32_ty,llvm_v32i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vlut4_128B : +Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; -class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v512i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v16i32_ty, - llvm_v16i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vmpyuhe_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; -class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v1024i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v32i32_ty, - llvm_v32i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vmpyuhe_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; -class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_i32_ty,llvm_i32_ty, - llvm_v32i32_ty,llvm_v16i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vrmpyub_rtt : +Hexagon_v32i32_v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; -class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_i32_ty,llvm_i32_ty, - llvm_v64i32_ty,llvm_v32i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vrmpyub_rtt_128B : +Hexagon_v64i32_v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; -class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v512i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v32i32_ty, - llvm_v16i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vmpsuhuhsat : +Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; -class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [], [llvm_v1024i1_ty,llvm_i32_ty, - llvm_i32_ty,llvm_v64i32_ty, - llvm_v32i32_ty], - [IntrWriteMem]>; +def int_hexagon_V6_vmpsuhuhsat_128B : +Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; -class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix> - : Hexagon_Intrinsic<GCCIntSuffix, - [llvm_v64i32_ty], [], - [IntrNoMem]>; +def int_hexagon_V6_vasruhubsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4) -// tag : V6_vscattermw -def int_hexagon_V6_vscattermw : -Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">; +def int_hexagon_V6_vasruhubsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4) -// tag : V6_vscattermw_128B -def int_hexagon_V6_vscattermw_128B : -Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">; +def int_hexagon_V6_vmpyuhe : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4) -// tag : V6_vscattermh -def int_hexagon_V6_vscattermh : -Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">; +def int_hexagon_V6_vmpyuhe_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4) -// tag : V6_vscattermh_128B -def int_hexagon_V6_vscattermh_128B : -Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">; +def int_hexagon_V6_vrmpyub_rtt_acc : +Hexagon_v32i32_v32i32v16i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4) -// tag : V6_vscattermw_add -def int_hexagon_V6_vscattermw_add : -Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">; +def int_hexagon_V6_vrmpyub_rtt_acc_128B : +Hexagon_v64i32_v64i32v32i32i64_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4) -// tag : V6_vscattermw_add_128B -def int_hexagon_V6_vscattermw_add_128B : -Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">; +def int_hexagon_V6_vasruwuhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4) -// tag : V6_vscattermh_add -def int_hexagon_V6_vscattermh_add : -Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">; +def int_hexagon_V6_vasruwuhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4) -// tag : V6_vscattermh_add_128B -def int_hexagon_V6_vscattermh_add_128B : -Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">; +def int_hexagon_V6_vmpabuu_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5) -// tag : V6_vscattermwq -def int_hexagon_V6_vscattermwq : -Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">; +def int_hexagon_V6_vmpabuu_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5) -// tag : V6_vscattermwq_128B -def int_hexagon_V6_vscattermwq_128B : -Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">; +def int_hexagon_V6_vprefixqw : +Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqw">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5) -// tag : V6_vscattermhq -def int_hexagon_V6_vscattermhq : -Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">; +def int_hexagon_V6_vprefixqw_128B : +Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5) -// tag : V6_vscattermhq_128B -def int_hexagon_V6_vscattermhq_128B : -Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">; +def int_hexagon_V6_vprefixqh : +Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqh">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4) -// tag : V6_vscattermhw -def int_hexagon_V6_vscattermhw : -Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">; +def int_hexagon_V6_vprefixqh_128B : +Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4) -// tag : V6_vscattermhw_128B -def int_hexagon_V6_vscattermhw_128B : -Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">; +def int_hexagon_V6_vprefixqb : +Hexagon_v16i32_v512i1_Intrinsic<"HEXAGON_V6_vprefixqb">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5) -// tag : V6_vscattermhwq -def int_hexagon_V6_vscattermhwq : -Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">; +def int_hexagon_V6_vprefixqb_128B : +Hexagon_v32i32_v1024i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5) -// tag : V6_vscattermhwq_128B -def int_hexagon_V6_vscattermhwq_128B : -Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">; +def int_hexagon_V6_vabsb : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4) -// tag : V6_vscattermhw_add -def int_hexagon_V6_vscattermhw_add : -Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">; +def int_hexagon_V6_vabsb_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4) -// tag : V6_vscattermhw_add_128B -def int_hexagon_V6_vscattermhw_add_128B : -Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">; +def int_hexagon_V6_vavgbrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; + +def int_hexagon_V6_vavgbrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; -// -// BUILTIN_INFO(HEXAGON.V6_vdd0,VD_ftype_,0) -// tag : V6_vdd0 def int_hexagon_V6_vdd0 : -Hexagon_v1024_Intrinsic<"HEXAGON_V6_vdd0">; +Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; -// -// BUILTIN_INFO(HEXAGON.V6_vdd0_128B,VD_ftype_,0) -// tag : V6_vdd0_128B def int_hexagon_V6_vdd0_128B : -Hexagon_V65_v2048_Intrinsic<"HEXAGON_V6_vdd0_128B">; +Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; + +def int_hexagon_V6_vmpabuu : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; + +def int_hexagon_V6_vmpabuu_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; + +def int_hexagon_V6_vabsb_sat : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; + +def int_hexagon_V6_vabsb_sat_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; + diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index dabf37e2887..10baca50e54 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -312,8 +312,6 @@ include "HexagonPatternsHVX.td" include "HexagonPatternsV65.td" include "HexagonDepMappings.td" include "HexagonIntrinsics.td" -include "HexagonMapAsm2IntrinV62.gen.td" -include "HexagonMapAsm2IntrinV65.gen.td" def HexagonInstrInfo : InstrInfo; diff --git a/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td new file mode 100644 index 00000000000..65cca41ce1a --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -0,0 +1,3307 @@ +//===----------------------------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Automatically generated file, please consult code owner before editing. +//===----------------------------------------------------------------------===// + + +// V5 Scalar Instructions. + +def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1), + (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2), + (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1), + (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred:$src2), + (S2_asr_i_r IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred:$src2), + (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred:$src2), + (A4_combineri IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1), + (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1), + (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1), + (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2), + (C4_cmplte IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred:$src2), + (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1), + (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abssat IntRegs:$src1), + (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2), + (C2_cmpgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2), + (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred:$src2), + (A4_cmphgtui IntRegs:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2), + (C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2), + (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1), + (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2), + (A4_cmpheq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3), + (S2_extractup DoubleRegs:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2), + (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1), + (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_not PredRegs:$src1), + (C2_not PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1), + (C2_tfrpr PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2), + (A4_cmpbgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred:$src2), + (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2), + (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2), + (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2), + (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2), + (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgti IntRegs:$src1, s8_0ImmPred:$src2), + (A4_cmpbgti IntRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2), + (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred:$src2), + (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2), + (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1), + (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (A2_pxorf PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred:$src2), + (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred:$src2), + (S2_asl_i_r IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1), + (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_all8 PredRegs:$src1), + (C2_all8 PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2), + (C2_bitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysip IntRegs:$src1, u32_0ImmPred:$src2), + (M2_mpysip IntRegs:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2), + (M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_boundscheck IntRegs:$src1, DoubleRegs:$src2), + (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_fastcorner9 PredRegs:$src1, PredRegs:$src2), + (C4_fastcorner9 PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2), + (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1), + (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_subi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1), + (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2), + (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2), + (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3, u5_0ImmPred:$src4), + (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3, u5_0ImmPred:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2), + (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred:$src2), + (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1), + (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred:$src2), + (C2_cmpgtui IntRegs:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1), + (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1), + (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1), + (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_any8 PredRegs:$src1), + (C2_any8 PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2), + (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred:$src2), + (S2_togglebit_i IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1), + (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1), + (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2), + (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred:$src2), + (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred:$src1), + (A2_tfrsi s32_0ImmPred:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2), + (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred:$src2), + (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred:$src2), + (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2), + (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred:$src2), + (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2), + (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2), + (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negsat IntRegs:$src1), + (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2), + (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1), + (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2), + (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addi u32_0ImmPred:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2), + (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_tfrpcp DoubleRegs:$src1), + (A4_tfrpcp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1), + (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxth IntRegs:$src1), + (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred:$src2), + (C4_cmpneqi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1), + (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2), + (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2), + (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred:$src2), + (C2_bitsclri IntRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (A4_addp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2), + (C2_xor PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1), + (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1), + (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1), + (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxth IntRegs:$src1), + (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1), + (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1), + (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1), + (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2), + (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1), + (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3), + (S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2), + (S2_tstbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3), + (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred:$src2), + (S2_tstbit_i IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2), + (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2), + (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1), + (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred:$src2), + (C2_cmpeqi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2), + (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred:$src2), + (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1), + (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred:$src3), + (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2), + (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1), + (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1), + (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred:$src2), + (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1), + (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2), + (C2_andn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred:$src2), + (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred:$src2), + (A4_round_ri IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2), + (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2), + (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineii s8_0ImmPred:$src1, u32_0ImmPred:$src2), + (A4_combineii s8_0ImmPred:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineir s32_0ImmPred:$src1, IntRegs:$src2), + (A4_combineir s32_0ImmPred:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2), + (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1), + (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2), + (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_ori_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2), + (C4_nbitsset IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2), + (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2), + (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred:$src1), + (F2_sfimm_p u10_0ImmPred:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred:$src1), + (F2_sfimm_n u10_0ImmPred:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1), + (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred:$src2), + (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2), + (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1), + (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2), + (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2), + (F2_sfcmpge IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2), + (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2), + (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2), + (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1), + (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1), + (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2), + (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred:$src2), + (C4_cmplteui IntRegs:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_addi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_tfrcpp CtrRegs64:$src1), + (A4_tfrcpp CtrRegs64:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred:$src2), + (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred:$src2), + (A4_cmphgti IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2), + (A4_cmphgtu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_subi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sath IntRegs:$src1), + (A2_sath IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satb IntRegs:$src1), + (A2_satb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3, u6_0ImmPred:$src4), + (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3, u6_0ImmPred:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_asrh IntRegs:$src1), + (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2), + (C2_or PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2), + (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2), + (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfinvsqrta IntRegs:$src1), + (F2_sfinvsqrta IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1), + (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2), + (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2), + (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_aslh IntRegs:$src1), + (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1), + (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1), + (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3), + (C2_muxri PredRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1), + (C2_pxfer_map PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2), + (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred:$src1, IntRegs:$src2, u6_0ImmPred:$src3), + (M4_mpyri_addi u32_0ImmPred:$src1, IntRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_andi_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3), + (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrcrr CtrRegs:$src1), + (A2_tfrcrr CtrRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3), + (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2), + (C2_orn PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2), + (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_mask PredRegs:$src1), + (C2_mask PredRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2), + (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrrcr IntRegs:$src1), + (A2_tfrrcr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2), + (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1), + (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_andi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2), + (C2_cmpgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1), + (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1), + (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred:$src2), + (F2_sfclass IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred:$src3), + (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred:$src2), + (A2_addi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1), + (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2), + (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1), + (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1), + (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1), + (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1), + (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2), + (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (A4_subp_c DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2), + (C2_vitpack PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2), + (C4_nbitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2), + (C2_and PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1), + (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3), + (S4_extractp DoubleRegs:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1), + (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred:$src2), + (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2), + (C4_cmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clb IntRegs:$src1), + (S2_clb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred:$src2), + (A4_bitspliti IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1), + (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred:$src1), + (F2_dfimm_n u10_0ImmPred:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2), + (A4_cmphgt IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred:$src1), + (F2_dfimm_p u10_0ImmPred:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred:$src2, IntRegs:$src3), + (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred:$src3), + (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cnacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2), + (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred:$src2), + (A2_andir IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfrecipa IntRegs:$src1, IntRegs:$src2), + (F2_sfrecipa IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combineii s32_0ImmPred:$src1, s8_0ImmPred:$src2), + (A2_combineii s32_0ImmPred:$src1, s8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2), + (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred:$src2), + (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred:$src2), + (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2), + (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2), + (C2_cmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1), + (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1), + (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satuh IntRegs:$src1), + (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satub IntRegs:$src1), + (A2_satub IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2), + (C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred:$src2), + (A2_tfrih IntRegs:$src1, u16_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred:$src2), + (A2_tfril IntRegs:$src1, u16_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3), + (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1), + (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1), + (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1), + (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2), + (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred:$src2, s8_0ImmPred:$src3), + (C2_muxii PredRegs:$src1, s32_0ImmPred:$src2, s8_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_swiz IntRegs:$src1), + (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2), + (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1), + (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2), + (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3), + (S4_extract IntRegs:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1), + (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfr IntRegs:$src1), + (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subri s32_0ImmPred:$src1, IntRegs:$src2), + (A2_subri s32_0ImmPred:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2), + (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_brev IntRegs:$src1), + (S2_brev IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred:$src2), + (S2_clrbit_i IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2), + (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3), + (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1), + (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred:$src4), + (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1), + (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred:$src2), + (A2_orir IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2), + (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred:$src2), + (M2_mpysmi IntRegs:$src1, m32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1), + (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1), + (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1), + (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1), + (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred:$src2), + (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1), + (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2), + (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1), + (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1), + (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2), + (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), + (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred:$src2), + (F2_dfclass DoubleRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1), + (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1), + (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred:$src2), + (C4_cmpltei IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2), + (C4_cmplteu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2), + (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2), + (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2), + (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred:$src2), + (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2), + (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_ori_lsr_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_lsli s6_0ImmPred:$src1, IntRegs:$src2), + (S4_lsli s6_0ImmPred:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1), + (C2_tfrrp IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abs IntRegs:$src1), + (A2_abs IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2), + (A4_cmpbeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1), + (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred:$src2), + (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1), + (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1), + (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2), + (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred:$src2), + (A4_cround_ri IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred:$src2), + (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2), + (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3), + (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3), + (S2_extractu IntRegs:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2), + (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred:$src2), + (S4_clbaddi IntRegs:$src1, s6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1), + (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2), + (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S4_addi_asl_ri u32_0ImmPred:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred:$src2), + (A4_cmpheqi IntRegs:$src1, s32_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1), + (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred:$src2), + (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred:$src2), + (S2_setbit_i IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2), + (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1), + (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2), + (C2_bitsclr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred:$src2), + (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred:$src2), + (C4_nbitsclri IntRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2), + (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV5]>; + +// V55 Scalar Instructions. + +def: Pat<(int_hexagon_A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A5_ACS DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV55]>; + +// V60 Scalar Instructions. + +def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred:$src2), + (S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred:$src2)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred:$src2), + (S6_rol_i_r IntRegs:$src1, u5_0ImmPred:$src2)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3), + (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3), + (S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred:$src3)>, Requires<[HasV60]>; + +// V62 Scalar Instructions. + +def: Pat<(int_hexagon_S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2), + (S6_vtrunehb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_V6_ldntnt0 IntRegs:$src1), + (V6_ldntnt0 IntRegs:$src1)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2), + (M6_vabsdiffub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2), + (S6_vtrunohb_ppp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_M6_vabsdiffb DoubleRegs:$src1, DoubleRegs:$src2), + (M6_vabsdiffb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2), + (A6_vminub_RdP DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV62]>; +def: Pat<(int_hexagon_S6_vsplatrbp IntRegs:$src1), + (S6_vsplatrbp IntRegs:$src1)>, Requires<[HasV62]>; + +// V65 Scalar Instructions. + +def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), + (A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV65]>; + +// V60 HVX Instructions. + +def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2), + (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrmpybusi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2), + (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2), + (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtran2x2_map_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vtran2x2_map HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2), + (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lo HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldu0 IntRegs:$src1), + (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldu0_128B IntRegs:$src1), + (V6_ldu0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsh HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsb HvxVR:$src1), + (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1), + (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vzh HvxVR:$src1), + (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1), + (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vzb HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2), + (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpybus_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyb HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslw HvxVR:$src1, IntRegs:$src2), + (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_hi HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubw HvxVR:$src1, HvxVR:$src2), + (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubw_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubw_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpybus_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1), + (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1), + (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2), + (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpybus_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ld0 IntRegs:$src1), + (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ld0_128B IntRegs:$src1), + (V6_ld0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldnt0 IntRegs:$src1), + (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldnt0_128B IntRegs:$src1), + (V6_ldnt0 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiowh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiowh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vd0 ), + (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vd0_128B ), + (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassign HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhb_dv_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdmpyhb_dv HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2), + (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyihb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffub HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth HvxVR:$src1, HvxVR:$src2), + (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb HvxVR:$src1, HvxVR:$src2), + (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnot HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2), + (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2), + (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1), + (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1), + (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybusi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4), + (V6_vrmpybusi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffw HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; + +// V62 HVX Instructions. + +def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2), + (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldcnpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldcnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2), + (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrb HvxVR:$src1, IntRegs:$src2), + (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldtp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldtp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldtp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2), + (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2), + (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldtpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldtpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldnpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldtnp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldtnp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldtnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrounduhub HvxVR:$src1, HvxVR:$src2), + (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrounduhub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldcp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldcp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldcp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduwsat HvxVR:$src1, HvxVR:$src2), + (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldtnpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldtnpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2), + (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2), + (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2), + (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2), + (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2), + (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldnp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldnp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_scalar2v2 IntRegs:$src1), + (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_scalar2v2_128B IntRegs:$src1), + (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddclbw HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddclbw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2), + (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldcpnt0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldcpnt0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_ldcnp0 PredRegs:$src1, IntRegs:$src2), + (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_ldcnp0_128B PredRegs:$src1, IntRegs:$src2), + (V6_ldcnp0 PredRegs:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4), + (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracci_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4), + (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred:$src4)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; + +// V65 HVX Instructions. + +def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2), + (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), + (V6_vrmpybub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), + (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpauhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vrmpybub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2), + (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_128B HvxVR:$src1, DoubleRegs:$src2), + (V6_vrmpyub_rtt HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_rtt_acc_128B HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3), + (V6_vrmpyub_rtt_acc HvxWR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), + (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), + (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vprefixqh HvxQR:$src1), + (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vprefixqh_128B HvxQR:$src1), + (V6_vprefixqh HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), + (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), + (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), + (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), + (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdd0 ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdd0_128B ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), + (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), + (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), + (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 206e74983d2..9cab5748bef 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -6,726 +6,78 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// This is populated based on the following specs: -// Hexagon V2 Architecture -// Application-Level Specification -// 80-V9418-8 Rev. B -// March 4, 2008 -//===----------------------------------------------------------------------===// -class T_I_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID imm:$Is), - (MI imm:$Is)>; +// These intrinsic patterns are not auto-generated. class T_R_pat <InstHexagon MI, Intrinsic IntID> : Pat <(IntID I32:$Rs), (MI I32:$Rs)>; -class T_P_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs), - (MI I64:$Rs)>; - -class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> - : Pat<(IntID Imm1:$Is, Imm2:$It), - (MI Imm1:$Is, Imm2:$It)>; - -class T_RI_pat <InstHexagon MI, Intrinsic IntID, - PatLeaf ImmPred = PatLeaf<(i32 imm)>> - : Pat<(IntID I32:$Rs, ImmPred:$It), - (MI I32:$Rs, ImmPred:$It)>; - -class T_IR_pat <InstHexagon MI, Intrinsic IntID, - PatFrag ImmPred = PatLeaf<(i32 imm)>> - : Pat<(IntID ImmPred:$Is, I32:$Rt), - (MI ImmPred:$Is, I32:$Rt)>; - -class T_PI_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID I64:$Rs, imm:$It), - (MI I64:$Rs, imm:$It)>; - -class T_RP_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID I32:$Rs, I64:$Rt), - (MI I32:$Rs, I64:$Rt)>; - class T_RR_pat <InstHexagon MI, Intrinsic IntID> : Pat <(IntID I32:$Rs, I32:$Rt), (MI I32:$Rs, I32:$Rt)>; -class T_PP_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt), - (MI I64:$Rs, I64:$Rt)>; - -class T_QQ_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, I32:$Rt), - (MI (C2_tfrrp I32:$Rs), (C2_tfrrp I32:$Rt))>; - -class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2> - : Pat <(IntID I32:$Rp, Imm1:$Is, Imm2:$It), - (MI (C2_tfrrp I32:$Rp), Imm1:$Is, Imm2:$It)>; - -class T_QRR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rp, I32:$Rs, I32:$Rt), - (MI (C2_tfrrp I32:$Rp), I32:$Rs, I32:$Rt)>; - -class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> - : Pat <(IntID I32:$Rp, I32:$Rs, ImmPred:$Is), - (MI (C2_tfrrp I32:$Rp), I32:$Rs, ImmPred:$Is)>; - -class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred> - : Pat <(IntID I32:$Rp, ImmPred:$Is, I32:$Rs), - (MI (C2_tfrrp I32:$Rp), ImmPred:$Is, I32:$Rs)>; - -class T_QPP_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rp, I64:$Rs, I64:$Rt), - (MI (C2_tfrrp I32:$Rp), I64:$Rs, I64:$Rt)>; - -class T_RRI_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu), - (MI I32:$Rs, I32:$Rt, imm:$Iu)>; - -class T_RII_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu), - (MI I32:$Rs, imm:$It, imm:$Iu)>; - -class T_IRI_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu), - (MI imm:$It, I32:$Rs, imm:$Iu)>; - -class T_IRR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt), - (MI imm:$Is, I32:$Rs, I32:$Rt)>; - -class T_RIR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt), - (MI I32:$Rs, imm:$Is, I32:$Rt)>; - -class T_RRR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru), - (MI I32:$Rs, I32:$Rt, I32:$Ru)>; - -class T_PPI_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu), - (MI I64:$Rs, I64:$Rt, imm:$Iu)>; - -class T_PII_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu), - (MI I64:$Rs, imm:$It, imm:$Iu)>; - -class T_PPP_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru), - (MI I64:$Rs, I64:$Rt, I64:$Ru)>; - -class T_PPR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru), - (MI I64:$Rs, I64:$Rt, I32:$Ru)>; - -class T_PRR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru), - (MI I64:$Rs, I32:$Rt, I32:$Ru)>; - -class T_PPQ_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Rp), - (MI I64:$Rs, I64:$Rt, (C2_tfrrp I32:$Rp))>; - -class T_PR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I32:$Rt), - (MI I64:$Rs, I32:$Rt)>; - -class T_D_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID (F64:$Rs)), - (MI (F64:$Rs))>; - -class T_DI_pat <InstHexagon MI, Intrinsic IntID, - PatLeaf ImmPred = PatLeaf<(i32 imm)>> - : Pat<(IntID F64:$Rs, ImmPred:$It), - (MI F64:$Rs, ImmPred:$It)>; - -class T_F_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F32:$Rs), - (MI F32:$Rs)>; - -class T_FI_pat <InstHexagon MI, Intrinsic IntID, - PatLeaf ImmPred = PatLeaf<(i32 imm)>> - : Pat<(IntID F32:$Rs, ImmPred:$It), - (MI F32:$Rs, ImmPred:$It)>; - -class T_FF_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F32:$Rs, F32:$Rt), - (MI F32:$Rs, F32:$Rt)>; - -class T_DD_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F64:$Rs, F64:$Rt), - (MI F64:$Rs, F64:$Rt)>; - -class T_FFF_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru), - (MI F32:$Rs, F32:$Rt, F32:$Ru)>; - -class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, I32:$Rp), - (MI F32:$Rs, F32:$Rt, F32:$Ru, (C2_tfrrp I32:$Rp))>; - -class T_Q_RI_pat <InstHexagon MI, Intrinsic IntID, - PatLeaf ImmPred = PatLeaf<(i32 imm)>> - : Pat<(IntID I32:$Rs, ImmPred:$It), - (C2_tfrpr (MI I32:$Rs, ImmPred:$It))>; - -class T_Q_RR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rs, I32:$Rt), - (C2_tfrpr (MI I32:$Rs, I32:$Rt))>; - -class T_Q_RP_pat <InstHexagon MI, Intrinsic IntID> +class T_RP_pat <InstHexagon MI, Intrinsic IntID> : Pat <(IntID I32:$Rs, I64:$Rt), - (C2_tfrpr (MI I32:$Rs, I64:$Rt))>; - -class T_Q_PR_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I32:$Rt), - (C2_tfrpr (MI I64:$Rs, I32:$Rt))>; - -class T_Q_PI_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID I64:$Rs, imm:$It), - (C2_tfrpr (MI I64:$Rs, imm:$It))>; - -class T_Q_PP_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I64:$Rs, I64:$Rt), - (C2_tfrpr (MI I64:$Rs, I64:$Rt))>; - -class T_Q_Q_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rp), - (C2_tfrpr (MI (C2_tfrrp I32:$Rp)))>; - -class T_Q_QQ_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rp, I32:$Rq), - (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq)))>; - -class T_Q_FF_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F32:$Rs, F32:$Rt), - (C2_tfrpr (MI F32:$Rs, F32:$Rt))>; - -class T_Q_DD_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F64:$Rs, F64:$Rt), - (C2_tfrpr (MI F64:$Rs, F64:$Rt))>; - -class T_Q_FI_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F32:$Rs, imm:$It), - (C2_tfrpr (MI F32:$Rs, imm:$It))>; - -class T_Q_DI_pat <InstHexagon MI, Intrinsic IntID> - : Pat<(IntID F64:$Rs, imm:$It), - (C2_tfrpr (MI F64:$Rs, imm:$It))>; - -class T_Q_QQQ_pat <InstHexagon MI, Intrinsic IntID> - : Pat <(IntID I32:$Rp, I32:$Rq, I32:$Rs), - (C2_tfrpr (MI (C2_tfrrp I32:$Rp), (C2_tfrrp I32:$Rq), - (C2_tfrrp I32:$Rs)))>; - -//===----------------------------------------------------------------------===// -// MPYS / Multipy signed/unsigned halfwords -//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -//===----------------------------------------------------------------------===// - -def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>; -def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>; -def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>; -def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>; -def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>; -def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>; -def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>; -def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>; - -def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>; -def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>; -def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>; -def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>; -def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>; -def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>; -def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>; -def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>; - -def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>; -def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>; -def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>; -def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>; -def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>; -def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>; -def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>; -def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>; - -def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>; -def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>; -def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>; -def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>; -def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>; -def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>; -def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>; -def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>; - -def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>; -def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>; -def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>; -def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>; -def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>; -def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>; -def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>; -def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>; - - -//===----------------------------------------------------------------------===// -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the accumulator. -//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>; -def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>; -def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>; -def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>; -def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>; -def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>; -def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>; -def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>; - -def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>; -def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>; -def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>; -def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>; -def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>; -def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>; -def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>; -def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>; - -def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>; -def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>; -def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>; -def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>; -def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>; -def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>; -def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>; -def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>; - -def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>; -def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>; -def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>; -def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>; -def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>; -def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>; -def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>; -def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>; - -def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>; -def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>; -def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>; -def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>; -def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>; -def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>; -def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>; -def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>; - -def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>; -def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>; -def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>; -def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>; -def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>; -def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>; -def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>; -def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>; - - -//===----------------------------------------------------------------------===// -// Multiply signed/unsigned halfwords with and without saturation and rounding -// into a 64-bits destination register. -//===----------------------------------------------------------------------===// - -def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>; -def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>; -def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>; -def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>; -def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>; -def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>; -def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>; -def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>; - -def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>; -def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>; -def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>; -def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>; -def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>; -def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>; -def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>; -def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>; - -def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>; -def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>; -def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>; -def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>; -def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>; -def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>; -def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>; -def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>; - -//===----------------------------------------------------------------------===// -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the 64-bit destination register. -//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>; -def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>; -def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>; -def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>; - -def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>; -def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>; -def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>; -def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>; - -def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>; -def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>; -def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>; -def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>; - -def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>; -def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>; -def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>; -def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>; - -def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>; -def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>; -def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>; -def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>; - -def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>; -def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>; -def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>; -def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>; - -def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>; -def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>; -def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>; -def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>; - -def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>; -def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>; -def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>; -def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>; - -// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat -def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>; -def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>; - -// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat -def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>; -def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>; - -// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat -def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>; -def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>; - -// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat -def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>; -def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>; - -//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PP_pat <M2_mmpyh_s0, int_hexagon_M2_mmpyh_s0>; -def : T_PP_pat <M2_mmpyh_s1, int_hexagon_M2_mmpyh_s1>; -def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>; -def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>; - -//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PP_pat <M2_mmpyl_s0, int_hexagon_M2_mmpyl_s0>; -def : T_PP_pat <M2_mmpyl_s1, int_hexagon_M2_mmpyl_s1>; -def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>; -def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>; - -//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PP_pat <M2_mmpyuh_s0, int_hexagon_M2_mmpyuh_s0>; -def : T_PP_pat <M2_mmpyuh_s1, int_hexagon_M2_mmpyuh_s1>; -def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>; -def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>; - -//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PP_pat <M2_mmpyul_s0, int_hexagon_M2_mmpyul_s0>; -def : T_PP_pat <M2_mmpyul_s1, int_hexagon_M2_mmpyul_s1>; -def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>; -def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>; - -// Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32) -def : T_PP_pat <A2_vraddub, int_hexagon_A2_vraddub>; -def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>; - -// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) -def : T_PP_pat <A2_vrsadub, int_hexagon_A2_vrsadub>; -def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>; - -// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) -def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>; - -// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) -def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>; - -// Vector reduce complex multiply real or imaginary: -// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) -def : T_PP_pat <M2_vrcmpyi_s0, int_hexagon_M2_vrcmpyi_s0>; -def : T_PP_pat <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>; -def : T_PPP_pat <M2_vrcmaci_s0, int_hexagon_M2_vrcmaci_s0>; -def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>; - -def : T_PP_pat <M2_vrcmpyr_s0, int_hexagon_M2_vrcmpyr_s0>; -def : T_PP_pat <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>; -def : T_PPP_pat <M2_vrcmacr_s0, int_hexagon_M2_vrcmacr_s0>; -def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>; - -// Vector reduce halfwords -// Rdd[+]=vrmpyh(Rss,Rtt) -def : T_PP_pat <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>; -def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>; - -//===----------------------------------------------------------------------===// -// Vector Multipy with accumulation -//===----------------------------------------------------------------------===// - -// Vector multiply word by signed half with accumulation -// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>; -def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>; -def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>; -def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>; -def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>; -def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>; -def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>; -def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>; - -// Vector multiply word by unsigned half with accumulation -// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat -def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>; -def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>; -def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>; -def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>; -def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>; -def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>; -def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>; -def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>; - -// Vector multiply even halfwords with accumulation -// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] -def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>; -def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>; -def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>; - -// Vector dual multiply with accumulation -// Rxx+=vdmpy(Rss,Rtt)[:sat] -def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>; -def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>; - -// Vector complex multiply real or imaginary with accumulation -// Rxx+=vcmpy[ir](Rss,Rtt):sat -def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>; -def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>; - -//===----------------------------------------------------------------------===// -// Add/Subtract halfword -// Rd=add(Rt.L,Rs.[HL])[:sat] -// Rd=sub(Rt.L,Rs.[HL])[:sat] -// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] -// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] -//===----------------------------------------------------------------------===// - -//Rd=add(Rt.L,Rs.[LH]) -def : T_RR_pat <A2_addh_l16_ll, int_hexagon_A2_addh_l16_ll>; -def : T_RR_pat <A2_addh_l16_hl, int_hexagon_A2_addh_l16_hl>; - -//Rd=add(Rt.L,Rs.[LH]):sat -def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>; -def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>; - -//Rd=sub(Rt.L,Rs.[LH]) -def : T_RR_pat <A2_subh_l16_ll, int_hexagon_A2_subh_l16_ll>; -def : T_RR_pat <A2_subh_l16_hl, int_hexagon_A2_subh_l16_hl>; - -//Rd=sub(Rt.L,Rs.[LH]):sat -def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>; -def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>; - -//Rd=add(Rt.[LH],Rs.[LH]):<<16 -def : T_RR_pat <A2_addh_h16_ll, int_hexagon_A2_addh_h16_ll>; -def : T_RR_pat <A2_addh_h16_lh, int_hexagon_A2_addh_h16_lh>; -def : T_RR_pat <A2_addh_h16_hl, int_hexagon_A2_addh_h16_hl>; -def : T_RR_pat <A2_addh_h16_hh, int_hexagon_A2_addh_h16_hh>; - -//Rd=sub(Rt.[LH],Rs.[LH]):<<16 -def : T_RR_pat <A2_subh_h16_ll, int_hexagon_A2_subh_h16_ll>; -def : T_RR_pat <A2_subh_h16_lh, int_hexagon_A2_subh_h16_lh>; -def : T_RR_pat <A2_subh_h16_hl, int_hexagon_A2_subh_h16_hl>; -def : T_RR_pat <A2_subh_h16_hh, int_hexagon_A2_subh_h16_hh>; - -//Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 -def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>; -def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>; -def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>; -def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>; - -//Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 -def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>; -def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>; -def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>; -def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>; - -// ALU64 / ALU / min max -def : T_RR_pat<A2_max, int_hexagon_A2_max>; -def : T_RR_pat<A2_min, int_hexagon_A2_min>; -def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>; -def : T_RR_pat<A2_minu, int_hexagon_A2_minu>; - -// Shift and accumulate -def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; -def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; -def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; -def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; -def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; -def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; - -def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; -def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; -def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; -def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; -def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; -def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; -def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; -def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; - -def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; -def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; -def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; -def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; -def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; -def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; - -def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; -def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; -def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; -def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; -def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; -def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; -def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; -def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; - -def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; -def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; -def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; -def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; -def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; -def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; -def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; -def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; - -def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; -def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; -def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; -def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; -def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; -def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; -def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; -def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; - -def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; -def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; -def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; -def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; -def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; -def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; -def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; -def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; - -def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; -def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; -def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; -def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; -def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; -def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; -def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; -def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; - -def : T_RRI_pat <S2_asr_i_r_nac, int_hexagon_S2_asr_i_r_nac>; -def : T_RRI_pat <S2_lsr_i_r_nac, int_hexagon_S2_lsr_i_r_nac>; -def : T_RRI_pat <S2_asl_i_r_nac, int_hexagon_S2_asl_i_r_nac>; -def : T_RRI_pat <S2_asr_i_r_acc, int_hexagon_S2_asr_i_r_acc>; -def : T_RRI_pat <S2_lsr_i_r_acc, int_hexagon_S2_lsr_i_r_acc>; -def : T_RRI_pat <S2_asl_i_r_acc, int_hexagon_S2_asl_i_r_acc>; - -def : T_RRI_pat <S2_asr_i_r_and, int_hexagon_S2_asr_i_r_and>; -def : T_RRI_pat <S2_lsr_i_r_and, int_hexagon_S2_lsr_i_r_and>; -def : T_RRI_pat <S2_asl_i_r_and, int_hexagon_S2_asl_i_r_and>; -def : T_RRI_pat <S2_asr_i_r_or, int_hexagon_S2_asr_i_r_or>; -def : T_RRI_pat <S2_lsr_i_r_or, int_hexagon_S2_lsr_i_r_or>; -def : T_RRI_pat <S2_asl_i_r_or, int_hexagon_S2_asl_i_r_or>; -def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>; -def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>; - -def : T_PPI_pat <S2_asr_i_p_nac, int_hexagon_S2_asr_i_p_nac>; -def : T_PPI_pat <S2_lsr_i_p_nac, int_hexagon_S2_lsr_i_p_nac>; -def : T_PPI_pat <S2_asl_i_p_nac, int_hexagon_S2_asl_i_p_nac>; -def : T_PPI_pat <S2_asr_i_p_acc, int_hexagon_S2_asr_i_p_acc>; -def : T_PPI_pat <S2_lsr_i_p_acc, int_hexagon_S2_lsr_i_p_acc>; -def : T_PPI_pat <S2_asl_i_p_acc, int_hexagon_S2_asl_i_p_acc>; - -def : T_PPI_pat <S2_asr_i_p_and, int_hexagon_S2_asr_i_p_and>; -def : T_PPI_pat <S2_lsr_i_p_and, int_hexagon_S2_lsr_i_p_and>; -def : T_PPI_pat <S2_asl_i_p_and, int_hexagon_S2_asl_i_p_and>; -def : T_PPI_pat <S2_asr_i_p_or, int_hexagon_S2_asr_i_p_or>; -def : T_PPI_pat <S2_lsr_i_p_or, int_hexagon_S2_lsr_i_p_or>; -def : T_PPI_pat <S2_asl_i_p_or, int_hexagon_S2_asl_i_p_or>; -def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>; -def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>; - -def : T_RRR_pat <S2_asr_r_r_nac, int_hexagon_S2_asr_r_r_nac>; -def : T_RRR_pat <S2_lsr_r_r_nac, int_hexagon_S2_lsr_r_r_nac>; -def : T_RRR_pat <S2_asl_r_r_nac, int_hexagon_S2_asl_r_r_nac>; -def : T_RRR_pat <S2_lsl_r_r_nac, int_hexagon_S2_lsl_r_r_nac>; -def : T_RRR_pat <S2_asr_r_r_acc, int_hexagon_S2_asr_r_r_acc>; -def : T_RRR_pat <S2_lsr_r_r_acc, int_hexagon_S2_lsr_r_r_acc>; -def : T_RRR_pat <S2_asl_r_r_acc, int_hexagon_S2_asl_r_r_acc>; -def : T_RRR_pat <S2_lsl_r_r_acc, int_hexagon_S2_lsl_r_r_acc>; - -def : T_RRR_pat <S2_asr_r_r_and, int_hexagon_S2_asr_r_r_and>; -def : T_RRR_pat <S2_lsr_r_r_and, int_hexagon_S2_lsr_r_r_and>; -def : T_RRR_pat <S2_asl_r_r_and, int_hexagon_S2_asl_r_r_and>; -def : T_RRR_pat <S2_lsl_r_r_and, int_hexagon_S2_lsl_r_r_and>; -def : T_RRR_pat <S2_asr_r_r_or, int_hexagon_S2_asr_r_r_or>; -def : T_RRR_pat <S2_lsr_r_r_or, int_hexagon_S2_lsr_r_r_or>; -def : T_RRR_pat <S2_asl_r_r_or, int_hexagon_S2_asl_r_r_or>; -def : T_RRR_pat <S2_lsl_r_r_or, int_hexagon_S2_lsl_r_r_or>; - -def : T_PPR_pat <S2_asr_r_p_nac, int_hexagon_S2_asr_r_p_nac>; -def : T_PPR_pat <S2_lsr_r_p_nac, int_hexagon_S2_lsr_r_p_nac>; -def : T_PPR_pat <S2_asl_r_p_nac, int_hexagon_S2_asl_r_p_nac>; -def : T_PPR_pat <S2_lsl_r_p_nac, int_hexagon_S2_lsl_r_p_nac>; -def : T_PPR_pat <S2_asr_r_p_acc, int_hexagon_S2_asr_r_p_acc>; -def : T_PPR_pat <S2_lsr_r_p_acc, int_hexagon_S2_lsr_r_p_acc>; -def : T_PPR_pat <S2_asl_r_p_acc, int_hexagon_S2_asl_r_p_acc>; -def : T_PPR_pat <S2_lsl_r_p_acc, int_hexagon_S2_lsl_r_p_acc>; - -def : T_PPR_pat <S2_asr_r_p_and, int_hexagon_S2_asr_r_p_and>; -def : T_PPR_pat <S2_lsr_r_p_and, int_hexagon_S2_lsr_r_p_and>; -def : T_PPR_pat <S2_asl_r_p_and, int_hexagon_S2_asl_r_p_and>; -def : T_PPR_pat <S2_lsl_r_p_and, int_hexagon_S2_lsl_r_p_and>; -def : T_PPR_pat <S2_asr_r_p_or, int_hexagon_S2_asr_r_p_or>; -def : T_PPR_pat <S2_lsr_r_p_or, int_hexagon_S2_lsr_r_p_or>; -def : T_PPR_pat <S2_asl_r_p_or, int_hexagon_S2_asl_r_p_or>; -def : T_PPR_pat <S2_lsl_r_p_or, int_hexagon_S2_lsl_r_p_or>; - -//******************************************************************* -// ALU32/ALU -//******************************************************************* -def : T_RR_pat<A2_add, int_hexagon_A2_add>; -def : T_RI_pat<A2_addi, int_hexagon_A2_addi>; -def : T_RR_pat<A2_sub, int_hexagon_A2_sub>; -def : T_IR_pat<A2_subri, int_hexagon_A2_subri>; -def : T_RR_pat<A2_and, int_hexagon_A2_and>; -def : T_RI_pat<A2_andir, int_hexagon_A2_andir>; -def : T_RR_pat<A2_or, int_hexagon_A2_or>; -def : T_RI_pat<A2_orir, int_hexagon_A2_orir>; -def : T_RR_pat<A2_xor, int_hexagon_A2_xor>; -def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>; + (MI I32:$Rs, I64:$Rt)>; + +def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt), + (A2_add IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, imm:$s16), + (A2_addi IntRegs:$Rs, imm:$s16)>; +def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt), + (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>; + +def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt), + (A2_sub IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_A2_subri imm:$s10, IntRegs:$Rs), + (A2_subri imm:$s10, IntRegs:$Rs)>; +def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt), + (A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt)>; + +def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt), + (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_M2_mpyui IntRegs:$Rs, IntRegs:$Rt), // Same as M2_mpyi + (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_M2_mpysmi IntRegs:$Rs, imm:$s9), + (M2_mpysmi IntRegs:$Rs, imm:$s9)>; +def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt), + (M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt), + (M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt)>; + +def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, imm:$u5), + (S2_asl_i_r IntRegs:$Rs, imm:$u5)>; +def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, imm:$u5), + (S2_lsr_i_r IntRegs:$Rs, imm:$u5)>; +def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, imm:$u5), + (S2_asr_i_r IntRegs:$Rs, imm:$u5)>; +def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$Rs, imm:$u6), + (S2_asl_i_p DoubleRegs:$Rs, imm:$u6)>; +def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$Rs, imm:$u6), + (S2_lsr_i_p DoubleRegs:$Rs, imm:$u6)>; +def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$Rs, imm:$u6), + (S2_asr_i_p DoubleRegs:$Rs, imm:$u6)>; + +def: Pat<(int_hexagon_A2_and IntRegs:$Rs, IntRegs:$Rt), + (A2_and IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_A2_andir IntRegs:$Rs, imm:$s10), + (A2_andir IntRegs:$Rs, imm:$s10)>; +def: Pat<(int_hexagon_A2_or IntRegs:$Rs, IntRegs:$Rt), + (A2_or IntRegs:$Rs, IntRegs:$Rt)>; +def: Pat<(int_hexagon_A2_orir IntRegs:$Rs, imm:$s10), + (A2_orir IntRegs:$Rs, imm:$s10)>; +def: Pat<(int_hexagon_A2_xor IntRegs:$Rs, IntRegs:$Rt), + (A2_xor IntRegs:$Rs, IntRegs:$Rt)>; + +def: Pat<(int_hexagon_A2_sxtb IntRegs:$Rs), + (A2_sxtb IntRegs:$Rs)>; +def: Pat<(int_hexagon_A2_sxth IntRegs:$Rs), + (A2_sxth IntRegs:$Rs)>; +def: Pat<(int_hexagon_A2_zxtb IntRegs:$Rs), + (A2_zxtb IntRegs:$Rs)>; +def: Pat<(int_hexagon_A2_zxth IntRegs:$Rs), + (A2_zxth IntRegs:$Rs)>; // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32) def : Pat <(int_hexagon_A2_not I32:$Rs), @@ -757,16 +109,6 @@ def : Pat <(int_hexagon_S5_vasrhrnd_goodsyntax I64:$Rs, u4_0ImmPred:$imm), def : Pat <(int_hexagon_S5_asrhub_rnd_sat_goodsyntax I64:$Rs, u4_0ImmPred:$imm), (S5_asrhub_rnd_sat I64:$Rs, (UDEC1 u4_0ImmPred:$imm))>; -// Transfer immediate -def : Pat <(int_hexagon_A2_tfril I32:$Rs, u16_0ImmPred:$Is), - (A2_tfril I32:$Rs, u16_0ImmPred:$Is)>; -def : Pat <(int_hexagon_A2_tfrih I32:$Rs, u16_0ImmPred:$Is), - (A2_tfrih I32:$Rs, u16_0ImmPred:$Is)>; - -// Transfer Register/immediate. -def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>; -def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>; - def ImmExt64: SDNodeXForm<imm, [{ int64_t V = N->getSExtValue(); return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64); @@ -783,49 +125,6 @@ def ImmExt64: SDNodeXForm<imm, [{ def : Pat<(int_hexagon_A2_tfrpi imm:$Is), (A2_tfrpi (ImmExt64 $Is))>; -// Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32) -def : Pat<(int_hexagon_A2_tfrp I64:$src), - (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>; - -//******************************************************************* -// ALU32/PERM -//******************************************************************* -// Combine -def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>; -def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>; -def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>; -def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>; - -def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32_0ImmPred, s8_0ImmPred>; - -// Mux -def : T_QRR_pat<C2_mux, int_hexagon_C2_mux>; -def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32_0ImmPred>; -def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32_0ImmPred>; -def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>; - -// Shift halfword -def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>; -def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>; - -// Sign/zero extend -def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>; -def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>; -def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>; -def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>; - -//******************************************************************* -// ALU32/PRED -//******************************************************************* -// Compare -def : T_Q_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>; -def : T_Q_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>; -def : T_Q_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>; - -def : T_Q_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32_0ImmPred>; -def : T_Q_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32_0ImmPred>; -def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32_0ImmPred>; - def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2), (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>; @@ -839,420 +138,6 @@ def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2), def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2), (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>; -//******************************************************************* -// ALU32/VH -//******************************************************************* -// Vector add, subtract, average halfwords -def: T_RR_pat<A2_svaddh, int_hexagon_A2_svaddh>; -def: T_RR_pat<A2_svaddhs, int_hexagon_A2_svaddhs>; -def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>; - -def: T_RR_pat<A2_svsubh, int_hexagon_A2_svsubh>; -def: T_RR_pat<A2_svsubhs, int_hexagon_A2_svsubhs>; -def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>; - -def: T_RR_pat<A2_svavgh, int_hexagon_A2_svavgh>; -def: T_RR_pat<A2_svavghs, int_hexagon_A2_svavghs>; -def: T_RR_pat<A2_svnavgh, int_hexagon_A2_svnavgh>; - -//******************************************************************* -// ALU64/ALU -//******************************************************************* -def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>; -def: T_RR_pat<A2_subsat, int_hexagon_A2_subsat>; -def: T_PP_pat<A2_addp, int_hexagon_A2_addp>; -def: T_PP_pat<A2_subp, int_hexagon_A2_subp>; - -def: T_PP_pat<A2_andp, int_hexagon_A2_andp>; -def: T_PP_pat<A2_orp, int_hexagon_A2_orp>; -def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>; - -def: T_Q_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>; -def: T_Q_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>; -def: T_Q_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>; - -def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>; -def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>; - -//******************************************************************* -// ALU64/VB -//******************************************************************* -// ALU64 - Vector add -def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddub>; -def : T_PP_pat <A2_vaddubs, int_hexagon_A2_vaddubs>; -def : T_PP_pat <A2_vaddh, int_hexagon_A2_vaddh>; -def : T_PP_pat <A2_vaddhs, int_hexagon_A2_vaddhs>; -def : T_PP_pat <A2_vadduhs, int_hexagon_A2_vadduhs>; -def : T_PP_pat <A2_vaddw, int_hexagon_A2_vaddw>; -def : T_PP_pat <A2_vaddws, int_hexagon_A2_vaddws>; - -// ALU64 - Vector average -def : T_PP_pat <A2_vavgub, int_hexagon_A2_vavgub>; -def : T_PP_pat <A2_vavgubr, int_hexagon_A2_vavgubr>; -def : T_PP_pat <A2_vavgh, int_hexagon_A2_vavgh>; -def : T_PP_pat <A2_vavghr, int_hexagon_A2_vavghr>; -def : T_PP_pat <A2_vavghcr, int_hexagon_A2_vavghcr>; -def : T_PP_pat <A2_vavguh, int_hexagon_A2_vavguh>; -def : T_PP_pat <A2_vavguhr, int_hexagon_A2_vavguhr>; - -def : T_PP_pat <A2_vavgw, int_hexagon_A2_vavgw>; -def : T_PP_pat <A2_vavgwr, int_hexagon_A2_vavgwr>; -def : T_PP_pat <A2_vavgwcr, int_hexagon_A2_vavgwcr>; -def : T_PP_pat <A2_vavguw, int_hexagon_A2_vavguw>; -def : T_PP_pat <A2_vavguwr, int_hexagon_A2_vavguwr>; - -// ALU64 - Vector negative average -def : T_PP_pat <A2_vnavgh, int_hexagon_A2_vnavgh>; -def : T_PP_pat <A2_vnavghr, int_hexagon_A2_vnavghr>; -def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>; -def : T_PP_pat <A2_vnavgw, int_hexagon_A2_vnavgw>; -def : T_PP_pat <A2_vnavgwr, int_hexagon_A2_vnavgwr>; -def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>; - -// ALU64 - Vector max -def : T_PP_pat <A2_vmaxh, int_hexagon_A2_vmaxh>; -def : T_PP_pat <A2_vmaxw, int_hexagon_A2_vmaxw>; -def : T_PP_pat <A2_vmaxub, int_hexagon_A2_vmaxub>; -def : T_PP_pat <A2_vmaxuh, int_hexagon_A2_vmaxuh>; -def : T_PP_pat <A2_vmaxuw, int_hexagon_A2_vmaxuw>; - -// ALU64 - Vector min -def : T_PP_pat <A2_vminh, int_hexagon_A2_vminh>; -def : T_PP_pat <A2_vminw, int_hexagon_A2_vminw>; -def : T_PP_pat <A2_vminub, int_hexagon_A2_vminub>; -def : T_PP_pat <A2_vminuh, int_hexagon_A2_vminuh>; -def : T_PP_pat <A2_vminuw, int_hexagon_A2_vminuw>; - -// ALU64 - Vector sub -def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubub>; -def : T_PP_pat <A2_vsububs, int_hexagon_A2_vsububs>; -def : T_PP_pat <A2_vsubh, int_hexagon_A2_vsubh>; -def : T_PP_pat <A2_vsubhs, int_hexagon_A2_vsubhs>; -def : T_PP_pat <A2_vsubuhs, int_hexagon_A2_vsubuhs>; -def : T_PP_pat <A2_vsubw, int_hexagon_A2_vsubw>; -def : T_PP_pat <A2_vsubws, int_hexagon_A2_vsubws>; - -// ALU64 - Vector compare bytes -def : T_Q_PP_pat <A2_vcmpbeq, int_hexagon_A2_vcmpbeq>; -def : T_Q_PP_pat <A4_vcmpbgt, int_hexagon_A4_vcmpbgt>; -def : T_Q_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>; - -// ALU64 - Vector compare halfwords -def : T_Q_PP_pat <A2_vcmpheq, int_hexagon_A2_vcmpheq>; -def : T_Q_PP_pat <A2_vcmphgt, int_hexagon_A2_vcmphgt>; -def : T_Q_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>; - -// ALU64 - Vector compare words -def : T_Q_PP_pat <A2_vcmpweq, int_hexagon_A2_vcmpweq>; -def : T_Q_PP_pat <A2_vcmpwgt, int_hexagon_A2_vcmpwgt>; -def : T_Q_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>; - -// ALU64 / VB / Vector mux. -def : T_QPP_pat <C2_vmux, int_hexagon_C2_vmux>; - -// MPY - Multiply and use full result -// Rdd = mpy[u](Rs, Rt) -def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>; -def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>; - -// Complex multiply real or imaginary -def : T_RR_pat <M2_cmpyi_s0, int_hexagon_M2_cmpyi_s0>; -def : T_RR_pat <M2_cmpyr_s0, int_hexagon_M2_cmpyr_s0>; - -// Complex multiply -def : T_RR_pat <M2_cmpys_s0, int_hexagon_M2_cmpys_s0>; -def : T_RR_pat <M2_cmpysc_s0, int_hexagon_M2_cmpysc_s0>; -def : T_RR_pat <M2_cmpys_s1, int_hexagon_M2_cmpys_s1>; -def : T_RR_pat <M2_cmpysc_s1, int_hexagon_M2_cmpysc_s1>; - -// Vector multiply halfwords -// Rdd=vmpyh(Rs,Rt)[:<<1]:sat -def : T_RR_pat <M2_vmpy2s_s0, int_hexagon_M2_vmpy2s_s0>; -def : T_RR_pat <M2_vmpy2s_s1, int_hexagon_M2_vmpy2s_s1>; - -// Rxx[+-]= mpy[u](Rs,Rt) -def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>; -def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>; -def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>; -def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>; - -// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat -def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>; -def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>; -def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>; -def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>; - -// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat -def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>; -def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>; -def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>; -def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>; - -// Rxx+=cmpy[ir](Rs,Rt) -def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>; -def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>; - -// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] -def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>; -def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>; -def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>; - -//******************************************************************* -// CR -//******************************************************************* -def: T_Q_Q_pat<C2_not, int_hexagon_C2_not>; -def: T_Q_Q_pat<C2_all8, int_hexagon_C2_all8>; -def: T_Q_Q_pat<C2_any8, int_hexagon_C2_any8>; -def: T_Q_Q_pat<C2_pxfer_map, int_hexagon_C2_pxfer_map>; - -def: T_Q_QQ_pat<C2_and, int_hexagon_C2_and>; -def: T_Q_QQ_pat<C2_andn, int_hexagon_C2_andn>; -def: T_Q_QQ_pat<C2_or, int_hexagon_C2_or>; -def: T_Q_QQ_pat<C2_orn, int_hexagon_C2_orn>; -def: T_Q_QQ_pat<C2_xor, int_hexagon_C2_xor>; - -// Multiply 32x32 and use lower result -def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>; -def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>; -def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>; - -// Subtract and accumulate -def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>; - -// Add and accumulate -def : T_RRR_pat <M2_acci, int_hexagon_M2_acci>; -def : T_RRR_pat <M2_nacci, int_hexagon_M2_nacci>; -def : T_RRI_pat <M2_accii, int_hexagon_M2_accii>; -def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>; - -// XOR and XOR with destination -def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>; - -// Vector dual multiply with round and pack -def : T_PP_pat <M2_vdmpyrs_s0, int_hexagon_M2_vdmpyrs_s0>; -def : T_PP_pat <M2_vdmpyrs_s1, int_hexagon_M2_vdmpyrs_s1>; - -// Vector multiply halfwords with round and pack -def : T_RR_pat <M2_vmpy2s_s0pack, int_hexagon_M2_vmpy2s_s0pack>; -def : T_RR_pat <M2_vmpy2s_s1pack, int_hexagon_M2_vmpy2s_s1pack>; - -// Multiply and use lower result -def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyi>; -def : T_RI_pat <M2_mpysmi, int_hexagon_M2_mpysmi>; - -// Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32) -def : T_RR_pat <M2_mpyi, int_hexagon_M2_mpyui>; - -// Multiply and use upper result -def : T_RR_pat <M2_mpy_up, int_hexagon_M2_mpy_up>; -def : T_RR_pat <M2_mpyu_up, int_hexagon_M2_mpyu_up>; -def : T_RR_pat <M2_hmmpyh_rs1, int_hexagon_M2_hmmpyh_rs1>; -def : T_RR_pat <M2_hmmpyl_rs1, int_hexagon_M2_hmmpyl_rs1>; -def : T_RR_pat <M2_dpmpyss_rnd_s0, int_hexagon_M2_dpmpyss_rnd_s0>; - -// Complex multiply with round and pack -// Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat -def : T_RR_pat <M2_cmpyrs_s0, int_hexagon_M2_cmpyrs_s0>; -def : T_RR_pat <M2_cmpyrs_s1, int_hexagon_M2_cmpyrs_s1>; -def : T_RR_pat <M2_cmpyrsc_s0, int_hexagon_M2_cmpyrsc_s0>; -def : T_RR_pat <M2_cmpyrsc_s1, int_hexagon_M2_cmpyrsc_s1>; - -//******************************************************************* -// STYPE/ALU -//******************************************************************* -def : T_P_pat <A2_absp, int_hexagon_A2_absp>; -def : T_P_pat <A2_negp, int_hexagon_A2_negp>; -def : T_P_pat <A2_notp, int_hexagon_A2_notp>; - -//******************************************************************* -// STYPE/BIT -//******************************************************************* - -// Count leading/trailing -def: T_R_pat<S2_cl0, int_hexagon_S2_cl0>; -def: T_P_pat<S2_cl0p, int_hexagon_S2_cl0p>; -def: T_R_pat<S2_cl1, int_hexagon_S2_cl1>; -def: T_P_pat<S2_cl1p, int_hexagon_S2_cl1p>; -def: T_R_pat<S2_clb, int_hexagon_S2_clb>; -def: T_P_pat<S2_clbp, int_hexagon_S2_clbp>; -def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>; -def: T_R_pat<S2_ct0, int_hexagon_S2_ct0>; -def: T_R_pat<S2_ct1, int_hexagon_S2_ct1>; - -// Compare bit mask -def: T_RR_pat<C2_bitsclr, int_hexagon_C2_bitsclr>; -def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>; -def: T_RR_pat<C2_bitsset, int_hexagon_C2_bitsset>; - -// Vector shuffle -def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>; -def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>; -def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>; -def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>; - -// Vector truncate -def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>; -def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>; - -// Linear feedback-shift Iteration. -def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>; - -// Vector align -// Need custom lowering -def : T_PPQ_pat <S2_valignrb, int_hexagon_S2_valignrb>; -def : T_PPI_pat <S2_valignib, int_hexagon_S2_valignib>; - -// Vector splice -def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>; -def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>; - -// Shift by immediate and add -def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>; - -// Extract bitfield -def : T_PII_pat<S2_extractup, int_hexagon_S2_extractup>; -def : T_RII_pat<S2_extractu, int_hexagon_S2_extractu>; -def : T_RP_pat <S2_extractu_rp, int_hexagon_S2_extractu_rp>; -def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>; - -// Insert bitfield -def : Pat <(int_hexagon_S2_insert_rp I32:$src1, I32:$src2, I64:$src3), - (S2_insert_rp I32:$src1, I32:$src2, I64:$src3)>; - -def : Pat<(i64 (int_hexagon_S2_insertp_rp I64:$src1, I64:$src2, I64:$src3)), - (i64 (S2_insertp_rp I64:$src1, I64:$src2, I64:$src3))>; - -def : Pat<(int_hexagon_S2_insert I32:$src1, I32:$src2, - u5_0ImmPred:$src3, u5_0ImmPred:$src4), - (S2_insert I32:$src1, I32:$src2, - u5_0ImmPred:$src3, u5_0ImmPred:$src4)>; - -def : Pat<(i64 (int_hexagon_S2_insertp I64:$src1, I64:$src2, - u6_0ImmPred:$src3, u6_0ImmPred:$src4)), - (i64 (S2_insertp I64:$src1, I64:$src2, - u6_0ImmPred:$src3, u6_0ImmPred:$src4))>; - -// Innterleave/deinterleave -def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>; -def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>; - -// Set/Clear/Toggle Bit -def: T_RI_pat<S2_setbit_i, int_hexagon_S2_setbit_i>; -def: T_RI_pat<S2_clrbit_i, int_hexagon_S2_clrbit_i>; -def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>; - -def: T_RR_pat<S2_setbit_r, int_hexagon_S2_setbit_r>; -def: T_RR_pat<S2_clrbit_r, int_hexagon_S2_clrbit_r>; -def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>; - -// Test Bit -def: T_Q_RI_pat<S2_tstbit_i, int_hexagon_S2_tstbit_i>; -def: T_Q_RR_pat<S2_tstbit_r, int_hexagon_S2_tstbit_r>; - -//******************************************************************* -// STYPE/COMPLEX -//******************************************************************* -// Vector Complex conjugate -def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>; - -// Vector Complex rotate -def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>; - -//******************************************************************* -// STYPE/PERM -//******************************************************************* - -// Vector saturate without pack -def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>; -def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>; -def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>; -def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>; - -//******************************************************************* -// STYPE/PRED -//******************************************************************* - -// Predicate transfer -def: Pat<(i32 (int_hexagon_C2_tfrpr I32:$Rs)), - (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>; -def: Pat<(i32 (int_hexagon_C2_tfrrp I32:$Rs)), - (i32 (C2_tfrpr (C2_tfrrp I32:$Rs)))>; - -// Mask generate from predicate -def: Pat<(i64 (int_hexagon_C2_mask I32:$Rs)), - (i64 (C2_mask (C2_tfrrp I32:$Rs)))>; - -// Viterbi pack even and odd predicate bits -def: T_QQ_pat<C2_vitpack, int_hexagon_C2_vitpack>; - -//******************************************************************* -// STYPE/SHIFT -//******************************************************************* - -def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>; -def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>; -def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>; - -def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>; -def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>; -def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>; -def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>; - -def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>; -def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>; -def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>; -def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>; - -def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>; -def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>; - -def : T_R_pat <S2_vsxtbh, int_hexagon_S2_vsxtbh>; -def : T_R_pat <S2_vzxtbh, int_hexagon_S2_vzxtbh>; -def : T_R_pat <S2_vsxthw, int_hexagon_S2_vsxthw>; -def : T_R_pat <S2_vzxthw, int_hexagon_S2_vzxthw>; -def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>; -def : T_R_pat <A2_sxtw, int_hexagon_A2_sxtw>; - -// Vector saturate and pack -def : T_R_pat <S2_svsathb, int_hexagon_S2_svsathb>; -def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>; -def : T_P_pat <S2_vsathub, int_hexagon_S2_vsathub>; -def : T_P_pat <S2_vsatwh, int_hexagon_S2_vsatwh>; -def : T_P_pat <S2_vsatwuh, int_hexagon_S2_vsatwuh>; -def : T_P_pat <S2_vsathb, int_hexagon_S2_vsathb>; - -def : T_P_pat <S2_vtrunohb, int_hexagon_S2_vtrunohb>; -def : T_P_pat <S2_vtrunehb, int_hexagon_S2_vtrunehb>; -def : T_P_pat <S2_vrndpackwh, int_hexagon_S2_vrndpackwh>; -def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>; -def : T_R_pat <S2_brev, int_hexagon_S2_brev>; -def : T_R_pat <S2_vsplatrb, int_hexagon_S2_vsplatrb>; - -def : T_R_pat <A2_abs, int_hexagon_A2_abs>; -def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>; -def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>; - -def : T_R_pat <A2_swiz, int_hexagon_A2_swiz>; - -def : T_P_pat <A2_sat, int_hexagon_A2_sat>; -def : T_R_pat <A2_sath, int_hexagon_A2_sath>; -def : T_R_pat <A2_satuh, int_hexagon_A2_satuh>; -def : T_R_pat <A2_satub, int_hexagon_A2_satub>; -def : T_R_pat <A2_satb, int_hexagon_A2_satb>; - -// Vector arithmetic shift right by immediate with truncate and pack. -def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>; - -def : T_RI_pat <S2_asr_i_r, int_hexagon_S2_asr_i_r>; -def : T_RI_pat <S2_lsr_i_r, int_hexagon_S2_lsr_i_r>; -def : T_RI_pat <S2_asl_i_r, int_hexagon_S2_asl_i_r>; -def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>; -def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax, - int_hexagon_S2_asr_i_r_rnd_goodsyntax>; - -// Shift left by immediate with saturation. -def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>; - //===----------------------------------------------------------------------===// // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions. //===----------------------------------------------------------------------===// @@ -1277,11 +162,8 @@ def SDEC3 : SDNodeXForm<imm, [{ // values from the 4th input operand. Please note that subtraction is not // needed for int_hexagon_S2_tableidxb_goodsyntax. -def : Pat <(int_hexagon_S2_tableidxb_goodsyntax I32:$src1, I32:$src2, - u4_0ImmPred:$src3, u5_0ImmPred:$src4), - (S2_tableidxb I32:$src1, I32:$src2, - u4_0ImmPred:$src3, u5_0ImmPred:$src4)>; - +def : S2op_tableidx_pat <int_hexagon_S2_tableidxb_goodsyntax, S2_tableidxb, + IdImm>; def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh, SDEC1>; def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw, @@ -1289,52 +171,6 @@ def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw, def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd, SDEC3>; -//******************************************************************* -// STYPE/VH -//******************************************************************* - -// Vector absolute value halfwords with and without saturation -// Rdd64=vabsh(Rss64)[:sat] -def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>; -def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>; - -// Vector shift halfwords by immediate -// Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4) -def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>; -def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>; -def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>; - -// Vector shift halfwords by register -// Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32) -def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>; -def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>; -def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>; -def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>; - -//******************************************************************* -// STYPE/VW -//******************************************************************* - -// Vector absolute value words with and without saturation -def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>; -def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>; - -// Vector shift words by immediate. -// Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5) -def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>; -def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>; -def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>; - -// Vector shift words by register. -// Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32) -def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>; -def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>; -def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>; -def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>; - -// Vector shift words with truncate and pack -def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>; - // Load/store locked. def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>; def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>; @@ -1370,10 +206,13 @@ def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>; multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> { def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + Requires<[UseHVX]>; + def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>; + (MI HvxQR:$src1, IntRegs:$src2, #0, HvxVR:$src3)>, + Requires<[UseHVX]>; } defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>; @@ -1398,5 +237,241 @@ def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>; def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>; def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>; -include "HexagonIntrinsicsV5.td" -include "HexagonIntrinsicsV60.td" +// +// Patterns for optimizing code generations for HVX. + +def u3_64_ImmPred : PatLeaf<(i32 imm), [{ + int64_t v = (int64_t)(64 - N->getSExtValue()); + return isUInt<3>(v); +}]>; + +def u3_128_ImmPred : PatLeaf<(i32 imm), [{ + int64_t v = (int64_t)(128 - N->getSExtValue()); + return isUInt<3>(v); +}]>; + +def SUB_64_VAL : SDNodeXForm<imm, [{ + int32_t Imm = N->getSExtValue(); + return CurDAG->getTargetConstant(64 - Imm, SDLoc(N), MVT::i32); +}]>; + +def SUB_128_VAL : SDNodeXForm<imm, [{ + int32_t Imm = N->getSExtValue(); + return CurDAG->getTargetConstant(128 - Imm, SDLoc(N), MVT::i32); +}]>; + +let AddedComplexity = 100 in { +def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>, + Requires<[UseHVX]>; + +def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))), + (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>, + Requires<[UseHVX]>; + +def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>, + Requires<[UseHVX]>; + +def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))), + (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>, + Requires<[UseHVX]>; +} + +def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))), + (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v512i1 (bitconvert (v32i16 HvxVR:$src1))), + (v512i1 (V6_vandvrt (v32i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v512i1 (bitconvert (v64i8 HvxVR:$src1))), + (v512i1 (V6_vandvrt (v64i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))), + (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v32i16 (bitconvert (v512i1 HvxQR:$src1))), + (v32i16 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v64i8 (bitconvert (v512i1 HvxQR:$src1))), + (v64i8 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))), + (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))), + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))), + (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(v128i8 (bitconvert (v1024i1 HvxQR:$src1))), + (v128i8 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +let AddedComplexity = 140 in { +def : Pat <(store (v512i1 HvxQR:$src1), (i32 IntRegs:$addr)), + (V6_vS32b_ai IntRegs:$addr, 0, + (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>, + Requires<[UseHVX]>; + +def : Pat <(v512i1 (load (i32 IntRegs:$addr))), + (v512i1 (V6_vandvrt + (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; + +def : Pat <(store (v1024i1 HvxQR:$src1), (i32 IntRegs:$addr)), + (V6_vS32b_ai IntRegs:$addr, 0, + (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>, + Requires<[UseHVX]>; + +def : Pat <(v1024i1 (load (i32 IntRegs:$addr))), + (v1024i1 (V6_vandvrt + (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>, + Requires<[UseHVX]>; +} + +def: Pat<(v64i16 (trunc v64i32:$Vdd)), + (v64i16 (V6_vpackwh_sat + (v32i32 (V6_hi HvxWR:$Vdd)), + (v32i32 (V6_lo HvxWR:$Vdd))))>, + Requires<[UseHVX]>; + +def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV55]>; + +multiclass T_VI_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2), + (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>, + Requires<[UseHVX]>; + + def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_0ImmPred:$src2), + (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>, + Requires<[UseHVX]>; +} + +multiclass T_VI_inv_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2), + (MI HvxVR:$src1, HvxVR:$src1, + (SUB_64_VAL u3_64_ImmPred:$src2))>, + Requires<[UseHVX]>; + + def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_128_ImmPred:$src2), + (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>, + Requires<[UseHVX]>; +} + +multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3), + (MI HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3)>, + Requires<[UseHVX]>; + + def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + u3_0ImmPred:$src3), + (MI HvxVR:$src1, HvxVR:$src2, + u3_0ImmPred:$src3)>, + Requires<[UseHVX]>; +} + +multiclass T_VVI_inv_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_64_ImmPred:$src3), + (MI HvxVR:$src1, HvxVR:$src2, + (SUB_64_VAL u3_64_ImmPred:$src3))>, + Requires<[UseHVX]>; + + def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + u3_128_ImmPred:$src3), + (MI HvxVR:$src1, HvxVR:$src2, + (SUB_128_VAL u3_128_ImmPred:$src3))>, + Requires<[UseHVX]>; +} + +multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, + Requires<[UseHVX]>; + + def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2, + IntRegs:$src3), + (MI HvxVR:$src1, HvxVR:$src2, + IntRegs:$src3)>, + Requires<[UseHVX]>; +} + +defm : T_VI_pat <V6_valignbi, int_hexagon_V6_vror>; +defm : T_VI_inv_pat <V6_vlalignbi, int_hexagon_V6_vror>; + +defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignb>; +defm : T_VVI_inv_pat <V6_vlalignbi, int_hexagon_V6_valignbi>; +defm : T_VVI_inv_pat <V6_vlalignbi, int_hexagon_V6_valignb>; +defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignbi>; +defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignb>; +defm : T_VVI_inv_pat <V6_valignbi, int_hexagon_V6_vlalignbi>; +defm : T_VVI_inv_pat <V6_valignbi, int_hexagon_V6_vlalignb>; +defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignbi>; + +def: Pat<(int_hexagon_V6_vd0), + (V6_vd0)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vd0_128B ), + (V6_vd0)>, Requires<[HasV60, UseHVX128B]>; + +def: Pat<(int_hexagon_V6_vdd0), + (V6_vdd0)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdd0_128B), + (V6_vdd0)>, Requires<[HasV65, UseHVX128B]>; + +def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX]>; +def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX]>; + +include "HexagonDepMapAsm2Intrin.td" diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll index 920ca9fddb4..1e2ea26a793 100644 --- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll @@ -3,10 +3,10 @@ ; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h) ; CHECK: } ; CHECK: { -; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}}) +; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2) ; CHECK: } ; CHECK: { -; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}}) +; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},#2) target triple = "hexagon" |
