diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/build-attributes.ll | 2 |
5 files changed, 15 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index cea97b5fa53..1dafff60921 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -154,10 +154,6 @@ def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", "Generate calls via indirect call " "instructions">; -def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", - "Reserve R9, making it unavailable as " - "GPR">; - def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", "Don't use movt/movw pairs for 32-bit " "imms">; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 9d2f0291076..3180480986d 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -40,6 +40,10 @@ using namespace llvm; #include "ARMGenSubtargetInfo.inc" static cl::opt<bool> +ReserveR9("arm-reserve-r9", cl::Hidden, + cl::desc("Reserve R9, making it unavailable as GPR")); + +static cl::opt<bool> UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden); @@ -140,7 +144,7 @@ void ARMSubtarget::initializeEnvironment() { UseSoftFloat = false; HasThumb2 = false; NoARM = false; - ReserveR9 = false; + IsR9Reserved = ReserveR9; NoMovt = false; SupportsTailCall = false; HasFP16 = false; @@ -208,10 +212,13 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { if (isTargetNaCl()) stackAlignment = 16; - if (isTargetMachO()) + if (isTargetMachO()) { + IsR9Reserved = ReserveR9 || !HasV6Ops; SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0); - else + } else { + IsR9Reserved = ReserveR9; SupportsTailCall = !isThumb1Only(); + } if (Align == DefaultAlign) { // Assume pre-ARMv6 doesn't support unaligned accesses. diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index b80dc7051f1..4f9bc372e4b 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -109,8 +109,8 @@ protected: /// NoARM - True if subtarget does not support ARM mode execution. bool NoARM; - /// ReserveR9 - True if R9 is not available as a general purpose register. - bool ReserveR9; + /// IsR9Reserved - True if R9 is a not available as general purpose register. + bool IsR9Reserved; /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of /// 32-bit imms (including global addresses). @@ -413,9 +413,7 @@ public: return isThumb1Only() && isMClass(); } - bool isR9Reserved() const { - return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; - } + bool isR9Reserved() const { return IsR9Reserved; } bool useMovt(const MachineFunction &MF) const; diff --git a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll index 81a6bb64971..9c0143be06c 100644 --- a/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll +++ b/llvm/test/CodeGen/ARM/2007-03-13-InstrSched.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ ; RUN: -mattr=+v6 | grep r9 ; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic \ -; RUN: -mattr=+v6,+reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer +; RUN: -mattr=+v6 -arm-reserve-r9 -ifcvt-limit=0 -stats 2>&1 | grep asm-printer ; | grep 35 define void @test(i32 %tmp56222, i32 %tmp36224, i32 %tmp46223, i32 %i.0196.0.ph, i32 %tmp8, i32* %tmp1011, i32** %tmp1, i32* %d2.1.out, i32* %d3.1.out, i32* %d0.1.out, i32* %d1.1.out) { diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll index 583c96b7444..29c702304a3 100644 --- a/llvm/test/CodeGen/ARM/build-attributes.ll +++ b/llvm/test/CodeGen/ARM/build-attributes.ll @@ -122,7 +122,7 @@ ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE +; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE ; ARMv8.1a (AArch32) ; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN |
