diff options
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/arm-tests.txt | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6087a6164ae..307ce885369 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1214,11 +1214,11 @@ static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, if (pred == 0xF) { Inst.setOpcode(ARM::BLXi); imm |= fieldFromInstruction32(Insn, 24, 1) << 1; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); return true; } - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false; return true; diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt index 43e6e07557f..52cd1126297 100644 --- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt +++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt @@ -248,6 +248,9 @@ # CHECK: stc2 p2, cr4, [r9], {157} 0x9d 0x42 0x89 0xfc +# CHECK: bne #-24 +0xfa 0xff 0xff 0x1a + # CHECK: blx #60 0x0f 0x00 0x00 0xfa |
