diff options
3 files changed, 41 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 0b605fd92a7..27bd191b93e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -159,6 +159,19 @@ bool AMDGPUInstructionSelector::selectG_GEP(MachineInstr &I) const { return selectG_ADD(I); } +bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const { + MachineBasicBlock *BB = I.getParent(); + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const MachineOperand &MO = I.getOperand(0); + const TargetRegisterClass *RC = + TRI.getConstrainedRegClassForOperand(MO, MRI); + if (RC) + RBI.constrainGenericRegister(MO.getReg(), *RC, MRI); + I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); + return true; +} + bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { unsigned IntrinsicID = I.getOperand(1).getIntrinsicID(); @@ -535,6 +548,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, return selectG_CONSTANT(I); case TargetOpcode::G_GEP: return selectG_GEP(I); + case TargetOpcode::G_IMPLICIT_DEF: + return selectG_IMPLICIT_DEF(I); case TargetOpcode::G_INTRINSIC: return selectG_INTRINSIC(I, CoverageInfo); case TargetOpcode::G_LOAD: diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 6c05f3cc0c1..afe142c23a0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -63,6 +63,7 @@ private: bool selectG_CONSTANT(MachineInstr &I) const; bool selectG_ADD(MachineInstr &I) const; bool selectG_GEP(MachineInstr &I) const; + bool selectG_IMPLICIT_DEF(MachineInstr &I) const; bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir new file mode 100644 index 00000000000..750beb47486 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN + +--- | + define amdgpu_kernel void @implicit_def(i32 addrspace(1)* %global0) {ret void} +... +--- + +name: implicit_def +legalized: true +regBankSelected: true + + +body: | + bb.0: + liveins: $vgpr3_vgpr4 + ; GCN-LABEL: name: implicit_def + ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 + ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GCN: FLAT_STORE_DWORD [[COPY]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr + %0:vgpr(s64) = COPY $vgpr3_vgpr4 + %1:vgpr(s32) = G_IMPLICIT_DEF + G_STORE %1, %0 :: (store 4 into %ir.global0) +... +--- |
