diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/mmx-schedule.ll | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 86ee44b4dec..1adcd519e42 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -717,14 +717,14 @@ def JWritePSHUFB: SchedWriteRes<[JFPU01, JVALU]> { let ResourceCycles = [1, 4]; let NumMicroOps = 3; } -def : InstRW<[JWritePSHUFB], (instrs PSHUFBrr, VPSHUFBrr)>; +def : InstRW<[JWritePSHUFB], (instrs MMX_PSHUFBrr, PSHUFBrr, VPSHUFBrr)>; def JWritePSHUFBLd: SchedWriteRes<[JLAGU, JFPU01, JVALU]> { let Latency = 7; let ResourceCycles = [1, 1, 4]; let NumMicroOps = 3; } -def : InstRW<[JWritePSHUFBLd, ReadAfterLd], (instrs PSHUFBrm, VPSHUFBrm)>; +def : InstRW<[JWritePSHUFBLd, ReadAfterLd], (instrs MMX_PSHUFBrm, PSHUFBrm, VPSHUFBrm)>; def JWriteVPERM: SchedWriteRes<[JFPU01, JFPX]> { let Latency = 2; diff --git a/llvm/test/CodeGen/X86/mmx-schedule.ll b/llvm/test/CodeGen/X86/mmx-schedule.ll index ad76dd5cc0d..a68db2d26df 100644 --- a/llvm/test/CodeGen/X86/mmx-schedule.ll +++ b/llvm/test/CodeGen/X86/mmx-schedule.ll @@ -4715,8 +4715,8 @@ define i64 @test_pshufb(x86_mmx %a0, x86_mmx %a1, x86_mmx *%a2) optsize { ; ; BTVER2-LABEL: test_pshufb: ; BTVER2: # %bb.0: -; BTVER2-NEXT: pshufb %mm1, %mm0 # sched: [1:0.50] -; BTVER2-NEXT: pshufb (%rdi), %mm0 # sched: [6:1.00] +; BTVER2-NEXT: pshufb %mm1, %mm0 # sched: [2:2.00] +; BTVER2-NEXT: pshufb (%rdi), %mm0 # sched: [7:2.00] ; BTVER2-NEXT: movq %mm0, %rax # sched: [1:0.50] ; BTVER2-NEXT: retq # sched: [4:1.00] ; |
