diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MipsFastISel.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll | 28 |
2 files changed, 29 insertions, 4 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 4b460551539..3b0edfe0b63 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -951,12 +951,9 @@ bool MipsFastISel::selectBranch(const Instruction *I) { // MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; - BI->getCondition(); // For now, just try the simplest case where it's fed by a compare. if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { - unsigned CondReg = createResultReg(&Mips::GPR32RegClass); - if (!emitCmp(CondReg, CI)) - return false; + unsigned CondReg = getRegForValue(CI); BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) .addReg(CondReg) .addMBB(TBB); diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll new file mode 100644 index 00000000000..ef8e1c2b014 --- /dev/null +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \ +; RUN: < %s -verify-machineinstrs | FileCheck %s + + +define i32 @foobar(i32*) { +bb0: +; CHECK-LABEL: foobar: +; CHECK: # %bb.0: # %bb0 +; CHECK: lw $[[REG0:[0-9]+]], 0($4) +; CHECK-NEXT: sltiu $[[REG1:[0-9]+]], $[[REG0]], 1 +; CHECK: sw $[[REG1]], [[SPILL:[0-9]+]]($sp) # 4-byte Folded Spill + %1 = load i32, i32* %0 , align 4 + %2 = icmp eq i32 %1, 0 + store atomic i32 0, i32* %0 monotonic, align 4 + br label %bb1 +bb1: +; CHECK: # %bb.1: # %bb1 +; CHECK-NEXT: lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload +; CHECK-NEXT: bgtz $[[REG2]], $BB0_3 + br i1 %2, label %bb2, label %bb3 +bb2: +; CHECK: $BB0_3: # %bb2 +; CHECK-NEXT: addiu $2, $zero, 1 + ret i32 1 +bb3: + ret i32 0 +} |
