summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--llvm/include/llvm/CodeGen/CommandFlags.h26
-rw-r--r--llvm/include/llvm/Support/CodeGen.h2
-rw-r--r--llvm/lib/Target/AArch64/AArch64TargetMachine.cpp2
-rw-r--r--llvm/lib/Target/AArch64/AArch64TargetMachine.h4
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp2
-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.h12
-rw-r--r--llvm/lib/Target/Mips/MipsTargetMachine.h4
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.h6
-rw-r--r--llvm/lib/Target/Sparc/SparcTargetMachine.cpp2
-rw-r--r--llvm/lib/Target/Sparc/SparcTargetMachine.h4
-rw-r--r--llvm/lib/Target/TargetMachine.cpp4
-rw-r--r--llvm/lib/Target/X86/X86TargetMachine.cpp2
-rw-r--r--llvm/lib/Target/XCore/XCoreTargetMachine.cpp2
13 files changed, 35 insertions, 37 deletions
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h
index 292744de25a..38d2e716673 100644
--- a/llvm/include/llvm/CodeGen/CommandFlags.h
+++ b/llvm/include/llvm/CodeGen/CommandFlags.h
@@ -46,20 +46,18 @@ MAttrs("mattr",
cl::desc("Target specific attributes (-mattr=help for details)"),
cl::value_desc("a1,+a2,-a3,..."));
-cl::opt<Reloc::Model>
-RelocModel("relocation-model",
- cl::desc("Choose relocation model"),
- cl::init(Reloc::Default),
- cl::values(
- clEnumValN(Reloc::Default, "default",
- "Target default relocation model"),
- clEnumValN(Reloc::Static, "static",
- "Non-relocatable code"),
- clEnumValN(Reloc::PIC_, "pic",
- "Fully relocatable, position independent code"),
- clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
- "Relocatable external references, non-relocatable code"),
- clEnumValEnd));
+cl::opt<Reloc::Model> RelocModel(
+ "relocation-model", cl::desc("Choose relocation model"),
+ cl::init(Reloc::Default),
+ cl::values(
+ clEnumValN(Reloc::Default, "default",
+ "Target default relocation model"),
+ clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
+ clEnumValN(Reloc::PIC_, "pic",
+ "Fully relocatable, position independent code"),
+ clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
+ "Relocatable external references, non-relocatable code"),
+ clEnumValEnd));
cl::opt<ThreadModel::Model>
TMModel("thread-model",
diff --git a/llvm/include/llvm/Support/CodeGen.h b/llvm/include/llvm/Support/CodeGen.h
index 6e31ef4cb10..4e926c966ed 100644
--- a/llvm/include/llvm/Support/CodeGen.h
+++ b/llvm/include/llvm/Support/CodeGen.h
@@ -19,7 +19,7 @@ namespace llvm {
// Relocation model types.
namespace Reloc {
- enum Model { Default, Static, PIC_, DynamicNoPIC };
+ enum Model { Default, Static, PIC_, DynamicNoPIC };
}
// Code model types.
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index c98056a619e..4d4e0dcc1ff 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -161,7 +161,7 @@ static void initReciprocals(AArch64TargetMachine& TM, AArch64Subtarget& ST)
TM.Options.Reciprocals.setDefaults("vec-divd", false, ExtraStepsD);
}
-/// TargetMachine ctor - Create an AArch64 architecture model.
+/// Create an AArch64 architecture model.
///
AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index aac98a205e0..e77ddd53044 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -49,7 +49,7 @@ private:
AArch64Subtarget Subtarget;
};
-// AArch64leTargetMachine - AArch64 little endian target machine.
+// AArch64 little endian target machine.
//
class AArch64leTargetMachine : public AArch64TargetMachine {
virtual void anchor();
@@ -60,7 +60,7 @@ public:
CodeGenOpt::Level OL);
};
-// AArch64beTargetMachine - AArch64 big endian target machine.
+// AArch64 big endian target machine.
//
class AArch64beTargetMachine : public AArch64TargetMachine {
virtual void anchor();
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index e352a35ff75..8a45da43720 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -172,7 +172,7 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
return Ret;
}
-/// TargetMachine ctor - Create an ARM architecture model.
+/// Create an ARM architecture model.
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 8ad1f3dc2c3..fb2bf427752 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -58,7 +58,7 @@ public:
}
};
-/// ARMTargetMachine - ARM target machine.
+/// ARM target machine.
///
class ARMTargetMachine : public ARMBaseTargetMachine {
virtual void anchor();
@@ -68,7 +68,7 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
};
-/// ARMLETargetMachine - ARM little endian target machine.
+/// ARM little endian target machine.
///
class ARMLETargetMachine : public ARMTargetMachine {
void anchor() override;
@@ -79,7 +79,7 @@ public:
CodeGenOpt::Level OL);
};
-/// ARMBETargetMachine - ARM big endian target machine.
+/// ARM big endian target machine.
///
class ARMBETargetMachine : public ARMTargetMachine {
void anchor() override;
@@ -90,7 +90,7 @@ public:
CodeGenOpt::Level OL);
};
-/// ThumbTargetMachine - Thumb target machine.
+/// Thumb target machine.
/// Due to the way architectures are handled, this represents both
/// Thumb-1 and Thumb-2.
///
@@ -103,7 +103,7 @@ public:
bool isLittle);
};
-/// ThumbLETargetMachine - Thumb little endian target machine.
+/// Thumb little endian target machine.
///
class ThumbLETargetMachine : public ThumbTargetMachine {
void anchor() override;
@@ -114,7 +114,7 @@ public:
CodeGenOpt::Level OL);
};
-/// ThumbBETargetMachine - Thumb big endian target machine.
+/// Thumb big endian target machine.
///
class ThumbBETargetMachine : public ThumbTargetMachine {
void anchor() override;
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 38b2ecff7d7..054f1de6e52 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -68,7 +68,7 @@ public:
const MipsABIInfo &getABI() const { return ABI; }
};
-/// MipsebTargetMachine - Mips32/64 big endian target machine.
+/// Mips32/64 big endian target machine.
///
class MipsebTargetMachine : public MipsTargetMachine {
virtual void anchor();
@@ -79,7 +79,7 @@ public:
CodeGenOpt::Level OL);
};
-/// MipselTargetMachine - Mips32/64 little endian target machine.
+/// Mips32/64 little endian target machine.
///
class MipselTargetMachine : public MipsTargetMachine {
virtual void anchor();
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 6496339519a..b49c01b5bfe 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -21,7 +21,7 @@
namespace llvm {
-/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
+/// Common code between 32-bit and 64-bit PowerPC targets.
///
class PPCTargetMachine : public LLVMTargetMachine {
public:
@@ -57,7 +57,7 @@ public:
};
};
-/// PPC32TargetMachine - PowerPC 32-bit target machine.
+/// PowerPC 32-bit target machine.
///
class PPC32TargetMachine : public PPCTargetMachine {
virtual void anchor();
@@ -68,7 +68,7 @@ public:
CodeGenOpt::Level OL);
};
-/// PPC64TargetMachine - PowerPC 64-bit target machine.
+/// PowerPC 64-bit target machine.
///
class PPC64TargetMachine : public PPCTargetMachine {
virtual void anchor();
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
index 6e75c634d0e..cf634d13dac 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -53,7 +53,7 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) {
return Ret;
}
-/// SparcTargetMachine ctor - Create an ILP32 architecture model
+/// Create an ILP32 architecture model
///
SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.h b/llvm/lib/Target/Sparc/SparcTargetMachine.h
index 4da9d2ccba9..1ce0774d25d 100644
--- a/llvm/lib/Target/Sparc/SparcTargetMachine.h
+++ b/llvm/lib/Target/Sparc/SparcTargetMachine.h
@@ -40,7 +40,7 @@ public:
}
};
-/// SparcV8TargetMachine - Sparc 32-bit target machine
+/// Sparc 32-bit target machine
///
class SparcV8TargetMachine : public SparcTargetMachine {
virtual void anchor();
@@ -51,7 +51,7 @@ public:
CodeGenOpt::Level OL);
};
-/// SparcV9TargetMachine - Sparc 64-bit target machine
+/// Sparc 64-bit target machine
///
class SparcV9TargetMachine : public SparcTargetMachine {
virtual void anchor();
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index 3a45b3343ca..06075e1cc7c 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -71,8 +71,8 @@ void TargetMachine::resetTargetOptions(const Function &F) const {
RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math");
}
-/// getRelocationModel - Returns the code generation relocation model. The
-/// choices are static, PIC, and dynamic-no-pic, and target default.
+/// Returns the code generation relocation model. The choices are static, PIC,
+/// and dynamic-no-pic, and target default.
Reloc::Model TargetMachine::getRelocationModel() const {
if (!CodeGenInfo)
return Reloc::Default;
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index e0f63de57a8..cde3197c58c 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -106,7 +106,7 @@ static std::string computeDataLayout(const Triple &TT) {
return Ret;
}
-/// X86TargetMachine ctor - Create an X86 target.
+/// Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
diff --git a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
index 2297bb314cc..3ffad052f88 100644
--- a/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
+++ b/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
@@ -21,7 +21,7 @@
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-/// XCoreTargetMachine ctor - Create an ILP32 architecture model
+/// Create an ILP32 architecture model
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
StringRef CPU, StringRef FS,
OpenPOWER on IntegriCloud