4 files changed, 43 insertions, 8 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index d95361eed15..aa4752c2bab 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -769,15 +769,17 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
     RxSBG.Input = N.getOperand(0);
     return true;
 
-  case ISD::ZERO_EXTEND: {
-    // Restrict the mask to the extended operand.
-    unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
-    if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
-      return false;
+  case ISD::ZERO_EXTEND:
+    if (RxSBG.Opcode != SystemZ::RNSBG) {
+      // Restrict the mask to the extended operand.
+      unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits();
+      if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize)))
+        return false;
 
-    RxSBG.Input = N.getOperand(0);
-    return true;
-  }
+      RxSBG.Input = N.getOperand(0);
+      return true;
+    }
+    // Fall through.
     
   case ISD::SIGN_EXTEND: {
     // Check that the extension bits are don't-care (i.e. are masked out
diff --git a/llvm/test/CodeGen/SystemZ/rnsbg-01.ll b/llvm/test/CodeGen/SystemZ/rnsbg-01.ll
index 666aeb21e8d..282810a7815 100644
--- a/llvm/test/CodeGen/SystemZ/rnsbg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/rnsbg-01.ll
@@ -255,3 +255,14 @@ define i64 @f22(i64 %a, i64 %b) {
   %and = and i64 %a, %rotlorb
   ret i64 %and
 }
+
+; Check the handling of zext and AND, which isn't suitable for RNSBG.
+define i64 @f23(i64 %a, i32 %b) {
+; CHECK-LABEL: f23:
+; CHECK-NOT: rnsbg
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %and = and i64 %a, %ext
+  ret i64 %and
+}
diff --git a/llvm/test/CodeGen/SystemZ/rosbg-01.ll b/llvm/test/CodeGen/SystemZ/rosbg-01.ll
index 0abacccba14..96ee870d42b 100644
--- a/llvm/test/CodeGen/SystemZ/rosbg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/rosbg-01.ll
@@ -108,3 +108,14 @@ define i64 @f11(i64 %a, i64 %b) {
   %or = or i64 %a, %andb
   ret i64 %or
 }
+
+; Check the handling of zext and OR, which can use ROSBG.
+define i64 @f12(i64 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: rosbg %r2, %r3, 32, 63, 0
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %or = or i64 %a, %ext
+  ret i64 %or
+}
diff --git a/llvm/test/CodeGen/SystemZ/rxsbg-01.ll b/llvm/test/CodeGen/SystemZ/rxsbg-01.ll
index 5491bff2ecd..339fe2a289f 100644
--- a/llvm/test/CodeGen/SystemZ/rxsbg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/rxsbg-01.ll
@@ -110,3 +110,14 @@ define i64 @f11(i64 %a, i64 %b) {
   %xor = xor i64 %a, %andb
   ret i64 %xor
 }
+
+; Check the handling of zext and XOR, which can use ROSBG.
+define i64 @f12(i64 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: rxsbg %r2, %r3, 32, 63, 0
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  %ext = zext i32 %add to i64
+  %xor = xor i64 %a, %ext
+  ret i64 %xor
+}