diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-fast-isel.ll | 10 |
2 files changed, 14 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index c3f6859f510..837a31f303f 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -2679,8 +2679,11 @@ bool AArch64FastISel::selectSelect(const Instruction *I) { return false; bool CondIsKill = hasTrivialKill(Cond); + const MCInstrDesc &II = TII.get(AArch64::ANDSWri); + CondReg = constrainOperandRegClass(II, CondReg, 1); + // Emit a TST instruction (ANDS wzr, reg, #imm). - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDSWri), + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, AArch64::WZR) .addReg(CondReg, getKillRegState(CondIsKill)) .addImm(AArch64_AM::encodeLogicalImmediate(1, 32)); diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll index a4d08f9016a..a1d51a54cd4 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -91,3 +91,13 @@ define void @t6() nounwind { } declare void @llvm.trap() nounwind + +define void @ands(i32* %addr) { +; CHECK-LABEL: ands: +; CHECK: tst [[COND:w[0-9]+]], #0x1 +; CHECK-NEXT: csel [[COND]], +entry: + %cond91 = select i1 undef, i32 1, i32 2 + store i32 %cond91, i32* %addr, align 4 + ret void +} |
