diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 21 |
2 files changed, 24 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index addf60a102d..628e1708684 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -130,6 +130,7 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, case TargetOpcode::G_AND: return AArch64::ANDXrr; case TargetOpcode::G_ADD: + case TargetOpcode::G_GEP: return AArch64::ADDXrr; case TargetOpcode::G_SUB: return AArch64::SUBXrr; @@ -340,7 +341,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { case TargetOpcode::G_SDIV: case TargetOpcode::G_UDIV: case TargetOpcode::G_ADD: - case TargetOpcode::G_SUB: { + case TargetOpcode::G_SUB: + case TargetOpcode::G_GEP: { // Reject the various things we don't support yet. if (unsupportedBinOp(I, RBI, MRI, TRI)) return false; diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 5dbdc7e101d..dd12bc833d6 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -70,6 +70,7 @@ define i32 @const_s32() { ret i32 42 } define i64 @const_s64() { ret i64 1234567890123 } + define i8* @gep(i8* %in) { ret i8* undef } ... --- @@ -1121,3 +1122,23 @@ body: | bb.0: %0(s64) = G_CONSTANT 1234567890123 ... + +--- +# CHECK-LABEL: name: gep +name: gep +legalized: true +regBankSelected: true +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + +# CHECK: body: +# CHECK: %1 = MOVi64imm 42 +# CHECK: %2 = ADDXrr %0, %1 +body: | + bb.0: + %0(p0) = COPY %x0 + %1(s64) = G_CONSTANT 42 + %2(p0) = G_GEP %0, %1(s64) +... |
