diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll | 92 |
2 files changed, 101 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 490bf5fb56c..32c0cbde3cf 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1933,6 +1933,15 @@ isProfitableToIfCvt(MachineBasicBlock &TBB, if (!TCycles) return false; + // In thumb code we often end up trading one branch for a IT block, and + // if we are cloning the instruction can increase code size. Prevent + // blocks with multiple predecesors from being ifcvted to prevent this + // cloning. + if (Subtarget.isThumb2() && TBB.getParent()->getFunction().hasMinSize()) { + if (TBB.pred_size() != 1 || FBB.pred_size() != 1) + return false; + } + // Attempt to estimate the relative costs of predication versus branching. // Here we scale up each component of UnpredCost to avoid precision issue when // scaling TCycles/FCycles by Probability. diff --git a/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll b/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll new file mode 100644 index 00000000000..146a2223c35 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/ifcvt-minsize.ll @@ -0,0 +1,92 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8m.main-none-none-eabi %s -o - -verify-machineinstrs | FileCheck %s + +declare i32 @fn(i32) #0 + +define i32 @f1(i32 %a) #0 { +; CHECK-LABEL: f1: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: mov r4, r0 +; CHECK-NEXT: bl fn +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: cbz r4, .LBB0_2 +; CHECK-NEXT: @ %bb.1: @ %return +; CHECK-NEXT: pop {r4, pc} +; CHECK-NEXT: .LBB0_2: @ %if.end +; CHECK-NEXT: bl fn +; CHECK-NEXT: adds r0, #1 +; CHECK-NEXT: pop {r4, pc} +entry: + %call = tail call i32 @fn(i32 %a) #2 + %tobool = icmp eq i32 %a, 0 + br i1 %tobool, label %if.end, label %return + +if.end: ; preds = %entry + %call1 = tail call i32 @fn(i32 0) #2 + %add = add nsw i32 %call1, 1 + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ] + ret i32 %retval.0 +} + +define i32 @f2(i32 %a) #0 { +; CHECK-LABEL: f2: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: mov r4, r0 +; CHECK-NEXT: bl fn +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: cmp r4, #1 +; CHECK-NEXT: bne .LBB1_2 +; CHECK-NEXT: @ %bb.1: @ %if.end +; CHECK-NEXT: bl fn +; CHECK-NEXT: adds r0, #1 +; CHECK-NEXT: .LBB1_2: @ %return +; CHECK-NEXT: pop {r4, pc} +entry: + %call = tail call i32 @fn(i32 %a) #2 + %tobool = icmp eq i32 %a, 1 + br i1 %tobool, label %if.end, label %return + +if.end: ; preds = %entry + %call1 = tail call i32 @fn(i32 0) #2 + %add = add nsw i32 %call1, 1 + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ %add, %if.end ], [ 0, %entry ] + ret i32 %retval.0 +} + +define void @f3(i32 %x) #0 { +; CHECK-LABEL: f3: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: cmp r0, #1 +; CHECK-NEXT: bne .LBB2_2 +; CHECK-NEXT: @ %bb.1: @ %t +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: movs r0, #0 +; CHECK-NEXT: bl fn +; CHECK-NEXT: pop.w {r7, lr} +; CHECK-NEXT: .LBB2_2: @ %f +; CHECK-NEXT: bx lr +entry: + %p = icmp eq i32 %x, 1 + br i1 %p, label %t, label %f + +t: + call i32 @fn(i32 0) + br label %f + +f: + ret void +} + +attributes #0 = { minsize nounwind optsize } + |
