diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PowerPCInstrInfo.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 19 |
2 files changed, 14 insertions, 12 deletions
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td index f80a31fc5dc..d762acd4f18 100644 --- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td @@ -275,8 +275,8 @@ def crbitm: Operand<i8> { def PHI : Pseudo<(ops variable_ops), "; PHI">; let isLoad = 1 in { -def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">; -def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">; +def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">; +def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">; } def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">; def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">; @@ -301,7 +301,8 @@ let Defs = [LR] in def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">; let isBranch = 1, isTerminator = 1 in { - def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false), + def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, + target:$true, target:$false), "; COND_BRANCH">; def B : IForm<18, 0, 0, (ops target:$func), "b $func">; //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">; diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 2ab048fa1c4..7d89ae09e48 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -145,8 +145,9 @@ class Ii32<bits<8> o, Format f, dag ops, string asm> def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE">; // PHI node. def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop -def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm), "#ADJCALLSTACKDOWN">; -def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm, i32imm), "#ADJCALLSTACKUP">; +def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN">; +def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP">; def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE">; def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF">; let isTerminator = 1 in @@ -1563,20 +1564,20 @@ class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm> // forms of instructions for doing these operations. Until the stackifier runs, // we prefer to be abstract. def FpMOV : FPI<0, Pseudo, SpecialFP, - (ops RFP, RFP), "">; // f1 = fmov f2 + (ops RFP:$dst, RFP:$src), "">; // f1 = fmov f2 def FpADD : FPI<0, Pseudo, TwoArgFP , - (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3 + (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fadd f2, f3 def FpSUB : FPI<0, Pseudo, TwoArgFP , - (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3 + (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fsub f2, f3 def FpMUL : FPI<0, Pseudo, TwoArgFP , - (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3 + (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fmul f2, f3 def FpDIV : FPI<0, Pseudo, TwoArgFP , - (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3 + (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fdiv f2, f3 -def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, +def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$dst), "">, Imp<[ST0], []>; // FPR = ST(0) -def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, +def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$src), "">, Imp<[], [ST0]>; // ST(0) = FPR // FADD reg, mem: Before stackification, these are represented by: |
