diff options
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/Verifier/test_g_add.mir | 11 |
2 files changed, 16 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index cf9cf75d592..6778dce3972 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -933,6 +933,11 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { Types.resize(std::max(TypeIdx + 1, Types.size())); const MachineOperand *MO = &MI->getOperand(I); + if (!MO->isReg()) { + report("generic instruction must use register operands", MI); + continue; + } + LLT OpTy = MRI->getType(MO->getReg()); // Don't report a type mismatch if there is no actual mismatch, only a // type missing, to reduce noise: @@ -1517,7 +1522,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { return; } if (SubIdx) { - report("Generic virtual register does not subregister index", MO, + report("Generic virtual register does not allow subregister index", MO, MONum); return; } diff --git a/llvm/test/Verifier/test_g_add.mir b/llvm/test/Verifier/test_g_add.mir index 54c470adc8a..9cd990bb8cc 100644 --- a/llvm/test/Verifier/test_g_add.mir +++ b/llvm/test/Verifier/test_g_add.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- @@ -25,4 +25,13 @@ body: | ; CHECK: Bad machine code: Explicit definition marked as use G_ADD %0, %1 + ; CHECK: Bad machine code: generic instruction must use register operands + %5:_(s32) = G_ADD %0, 1 + + %6:_(s64) = G_CONSTANT i64 0 + + ; CHECK: Bad machine code: Type mismatch in generic instruction + ; CHECK: Bad machine code: Generic virtual register does not allow subregister index + %8:_(s32) = G_ADD %6.sub_32:_(s64), %0 + ... |
