diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/DFAPacketizer.h | 1 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/DFAPacketizer.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 8 |
3 files changed, 6 insertions, 7 deletions
diff --git a/llvm/include/llvm/CodeGen/DFAPacketizer.h b/llvm/include/llvm/CodeGen/DFAPacketizer.h index a0826059e09..f9cdc2a469f 100644 --- a/llvm/include/llvm/CodeGen/DFAPacketizer.h +++ b/llvm/include/llvm/CodeGen/DFAPacketizer.h @@ -91,7 +91,6 @@ public: // API call is made to prune the dependence. class VLIWPacketizerList { protected: - const TargetMachine &TM; const MachineFunction &MF; const TargetInstrInfo *TII; diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp index 7bd578ff254..0a188c0935a 100644 --- a/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -126,8 +126,8 @@ void DefaultVLIWScheduler::schedule() { // VLIWPacketizerList Ctor VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA) - : TM(MF.getTarget()), MF(MF) { - TII = TM.getSubtargetImpl()->getInstrInfo(); + : MF(MF) { + TII = MF.getSubtarget().getInstrInfo(); ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget()); VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA); } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 522c810ba0f..e7296d65078 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -323,7 +323,7 @@ bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI, const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; const HexagonRegisterInfo *QRI = - (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo(); + (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo(); // Check for lr dependence if (DepReg == QRI->getRARegister()) { @@ -548,7 +548,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( return false; const HexagonRegisterInfo *QRI = - (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo(); + (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo(); const MCInstrDesc& MCID = PacketMI->getDesc(); // first operand is always the result @@ -722,7 +722,7 @@ bool HexagonPacketizerList::CanPromoteToNewValue( const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; const HexagonRegisterInfo *QRI = - (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo(); + (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo(); if (!QRI->Subtarget.hasV4TOps() || !QII->mayBeNewStore(MI)) return false; @@ -1004,7 +1004,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { const unsigned FrameSize = MF.getFrameInfo()->getStackSize(); const HexagonRegisterInfo *QRI = - (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo(); + (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo(); const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; // Inline asm cannot go in the packet. |
