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-rw-r--r--clang/lib/Headers/arm_acle.h9
-rw-r--r--clang/test/CodeGen/arm_acle.c24
2 files changed, 31 insertions, 2 deletions
diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h
index c51a5dcbef2..a0fd6894ab9 100644
--- a/clang/lib/Headers/arm_acle.h
+++ b/clang/lib/Headers/arm_acle.h
@@ -33,8 +33,15 @@
#if defined(__cplusplus)
extern "C" {
#endif
-
+
/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
+/* 8.3 Memory barriers */
+#if !defined(_MSC_VER)
+#define __dmb(i) __builtin_arm_dmb(i)
+#define __dsb(i) __builtin_arm_dsb(i)
+#define __isb(i) __builtin_arm_isb(i)
+#endif
+
/* 8.4 Hints */
#if !defined(_MSC_VER)
diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c
index 41ebe1504c5..e4d795a1542 100644
--- a/clang/test/CodeGen/arm_acle.c
+++ b/clang/test/CodeGen/arm_acle.c
@@ -3,8 +3,30 @@
#include <arm_acle.h>
-/* Hints */
+/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
+/* 8.3 Memory Barriers */
+// ARM-LABEL: test_dmb
+// AArch32: call void @llvm.arm.dmb(i32 1)
+// AArch64: call void @llvm.aarch64.dmb(i32 1)
+void test_dmb(void) {
+ __dmb(1);
+}
+
+// ARM-LABEL: test_dsb
+// AArch32: call void @llvm.arm.dsb(i32 2)
+// AArch64: call void @llvm.aarch64.dsb(i32 2)
+void test_dsb(void) {
+ __dsb(2);
+}
+
+// ARM-LABEL: test_isb
+// AArch32: call void @llvm.arm.isb(i32 3)
+// AArch64: call void @llvm.aarch64.isb(i32 3)
+void test_isb(void) {
+ __isb(3);
+}
+/* 8.4 Hints */
// ARM-LABEL: test_yield
// AArch32: call void @llvm.arm.hint(i32 1)
// AArch64: call void @llvm.aarch64.hint(i32 1)
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