diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index cea4c68f4d7..76b7f1079b1 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -554,10 +554,7 @@ def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> { } // BT. -// r,r/i. -def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>; - -def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mr")>; +// m,i. def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>; // BTR BTS BTC. @@ -568,7 +565,6 @@ def ZnWriteBTRSC : SchedWriteRes<[ZnALU]> { } def : InstRW<[ZnWriteBTRSC], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>; - // m,r,i. def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> { let Latency = 6; |
