diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fast-isel-shift.ll | 48 |
2 files changed, 51 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index f09f6003289..5c2daa1fdbe 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -3453,8 +3453,9 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, bool IsZext) { assert(RetVT.SimpleTy >= SrcVT.SimpleTy && "Unexpected source/return type pair."); - assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 || - SrcVT == MVT::i64) && "Unexpected source value type."); + assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || + SrcVT == MVT::i32 || SrcVT == MVT::i64) && + "Unexpected source value type."); assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || RetVT == MVT::i64) && "Unexpected return value type."); diff --git a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll index da8469c0ecd..e4a3b860d2e 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll @@ -1,5 +1,53 @@ ; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s +; CHECK-LABEL: lsl_zext_i1_i16 +; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 +define zeroext i16 @lsl_zext_i1_i16(i1 %b) { + %1 = zext i1 %b to i16 + %2 = shl i16 %1, 4 + ret i16 %2 +} + +; CHECK-LABEL: lsl_sext_i1_i16 +; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 +define signext i16 @lsl_sext_i1_i16(i1 %b) { + %1 = sext i1 %b to i16 + %2 = shl i16 %1, 4 + ret i16 %2 +} + +; CHECK-LABEL: lsl_zext_i1_i32 +; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 +define i32 @lsl_zext_i1_i32(i1 %b) { + %1 = zext i1 %b to i32 + %2 = shl i32 %1, 4 + ret i32 %2 +} + +; CHECK-LABEL: lsl_sext_i1_i32 +; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1 +define i32 @lsl_sext_i1_i32(i1 %b) { + %1 = sext i1 %b to i32 + %2 = shl i32 %1, 4 + ret i32 %2 +} + +; CHECK-LABEL: lsl_zext_i1_i64 +; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1 +define i64 @lsl_zext_i1_i64(i1 %b) { + %1 = zext i1 %b to i64 + %2 = shl i64 %1, 4 + ret i64 %2 +} + +; CHECK-LABEL: lsl_sext_i1_i64 +; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1 +define i64 @lsl_sext_i1_i64(i1 %b) { + %1 = sext i1 %b to i64 + %2 = shl i64 %1, 4 + ret i64 %2 +} + ; CHECK-LABEL: lslv_i8 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xff ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]] |
