diff options
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp | 5 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vec_shuffle.ll | 17 |
2 files changed, 20 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index 1e724106991..c0b9b2fc3e5 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -763,9 +763,10 @@ InstCombiner::EvaluateInDifferentElementOrder(Value *V, ArrayRef<int> Mask) { } } + // If element is not in Mask, no need to handle the operand 1 (element to + // be inserted). Just evaluate values in operand 0 according to Mask. if (!Found) - return UndefValue::get( - VectorType::get(V->getType()->getScalarType(), Mask.size())); + return EvaluateInDifferentElementOrder(I->getOperand(0), Mask); Value *V = EvaluateInDifferentElementOrder(I->getOperand(0), Mask); return InsertElementInst::Create(V, I->getOperand(1), diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll index 3ee43dc63a6..a409a911ef1 100644 --- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll +++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll @@ -228,3 +228,20 @@ define <4 x float> @test15b(<4 x float> %LHS, <4 x float> %RHS) { ret <4 x float> %tmp5 } +define <1 x i32> @test16a(i32 %ele) { +; CHECK-LABEL: @test16a( +; CHECK-NEXT: ret <1 x i32> <i32 2> + %tmp0 = insertelement <2 x i32> <i32 1, i32 undef>, i32 %ele, i32 1 + %tmp1 = shl <2 x i32> %tmp0, <i32 1, i32 1> + %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <1 x i32> <i32 0> + ret <1 x i32> %tmp2 +} + +define <4 x i8> @test16b(i8 %ele) { +; CHECK-LABEL: @test16b( +; CHECK-NEXT: ret <4 x i8> <i8 2, i8 2, i8 2, i8 2> + %tmp0 = insertelement <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 undef, i8 1>, i8 %ele, i32 6 + %tmp1 = shl <8 x i8> %tmp0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> + %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4> + ret <4 x i8> %tmp2 +}
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