diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 15 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/mul64-sext.ll | 28 |
2 files changed, 41 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index e618f64c00e..54e501a6638 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1275,9 +1275,13 @@ bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) { EVT T = Opc == ISD::SIGN_EXTEND ? N.getOperand(0).getValueType() : cast<VTSDNode>(N.getOperand(1))->getVT(); - if (T.getSizeInBits() != 32) + unsigned SW = T.getSizeInBits(); + if (SW == 32) + R = N.getOperand(0); + else if (SW < 32) + R = N; + else return false; - R = N.getOperand(0); break; } case ISD::LOAD: { @@ -1291,6 +1295,13 @@ bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) { R = N; break; } + case ISD::SRA: { + auto *S = dyn_cast<ConstantSDNode>(N.getOperand(1)); + if (!S || S->getZExtValue() != 32) + return false; + R = N; + break; + } default: return false; } diff --git a/llvm/test/CodeGen/Hexagon/mul64-sext.ll b/llvm/test/CodeGen/Hexagon/mul64-sext.ll index b16ae9932cc..d409e4de427 100644 --- a/llvm/test/CodeGen/Hexagon/mul64-sext.ll +++ b/llvm/test/CodeGen/Hexagon/mul64-sext.ll @@ -28,6 +28,34 @@ b2: ret i64 %v7 } +; CHECK-LABEL: mul_3 +; CHECK: r[[REG30:[0-9]+]] = sxth(r2) +; CHECK: r1:0 = mpy(r[[REG30]],r0) +; CHECK: jumpr r31 +define i64 @mul_3(i64 %a0, i64 %a1) #0 { +b2: + %v3 = shl i64 %a0, 32 + %v4 = ashr exact i64 %v3, 32 + %v5 = shl i64 %a1, 48 + %v6 = ashr exact i64 %v5, 48 + %v7 = mul nsw i64 %v6, %v4 + ret i64 %v7 +} + +; CHECK-LABEL: mul_4 +; CHECK: r[[REG40:[0-9]+]] = asrh(r2) +; CHECK: r1:0 = mpy(r1,r[[REG40]]) +; CHECK: jumpr r31 +define i64 @mul_4(i64 %a0, i64 %a1) #0 { +b2: + %v3 = ashr i64 %a0, 32 + %v4 = trunc i64 %a1 to i32 + %v5 = ashr i32 %v4, 16 + %v6 = sext i32 %v5 to i64 + %v7 = mul nsw i64 %v3, %v6 + ret i64 %v7 +} + ; CHECK-LABEL: mul_acc_1 ; CHECK: r5:4 += mpy(r2,r0) ; CHECK: r1:0 = combine(r5,r4) |
