diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4d1d8ae1cb7..2ba2934e007 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34337,24 +34337,8 @@ static bool canReduceVMulWidth(SDNode *N, SelectionDAG &DAG, ShrinkMode &Mode) { for (unsigned i = 0; i < 2; i++) { SDValue Opd = N->getOperand(i); - // DAG.ComputeNumSignBits return 1 for ISD::ANY_EXTEND, so we need to - // compute signbits for it separately. - if (Opd.getOpcode() == ISD::ANY_EXTEND) { - // For anyextend, it is safe to assume an appropriate number of leading - // sign/zero bits. - if (Opd.getOperand(0).getValueType().getVectorElementType() == MVT::i8) - SignBits[i] = 25; - else if (Opd.getOperand(0).getValueType().getVectorElementType() == - MVT::i16) - SignBits[i] = 17; - else - return false; - IsPositive[i] = true; - } else { - SignBits[i] = DAG.ComputeNumSignBits(Opd); - if (DAG.SignBitIsZero(Opd)) - IsPositive[i] = true; - } + SignBits[i] = DAG.ComputeNumSignBits(Opd); + IsPositive[i] = DAG.SignBitIsZero(Opd); } bool AllPositive = IsPositive[0] && IsPositive[1]; |
