diff options
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/risbg-01.ll | 15 |
2 files changed, 30 insertions, 5 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index f4a27733ce0..567a6b7451f 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -764,9 +764,22 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const { return true; } - case ISD::SIGN_EXTEND: - case ISD::ZERO_EXTEND: - case ISD::ANY_EXTEND: { + case ISD::ANY_EXTEND: + // Bits above the extended operand are don't-care. + RxSBG.Input = N.getOperand(0); + return true; + + case ISD::ZERO_EXTEND: { + // Restrict the mask to the extended operand. + unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); + if (!refineRxSBGMask(RxSBG, allOnes(InnerBitSize))) + return false; + + RxSBG.Input = N.getOperand(0); + return true; + } + + case ISD::SIGN_EXTEND: { // Check that the extension bits are don't-care (i.e. are masked out // by the final mask). unsigned InnerBitSize = N.getOperand(0).getValueType().getSizeInBits(); @@ -1064,6 +1077,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { case ISD::ROTL: case ISD::SHL: case ISD::SRL: + case ISD::ZERO_EXTEND: if (!ResNode) ResNode = tryRISBGZero(Node); break; diff --git a/llvm/test/CodeGen/SystemZ/risbg-01.ll b/llvm/test/CodeGen/SystemZ/risbg-01.ll index a4d11fdae5b..e303067e539 100644 --- a/llvm/test/CodeGen/SystemZ/risbg-01.ll +++ b/llvm/test/CodeGen/SystemZ/risbg-01.ll @@ -457,11 +457,22 @@ define i64 @f40(i64 %foo, i64 *%dest) { ret i64 %and } +; Check a case where the result is zero-extended. +define i64 @f41(i32 %a) { +; CHECK-LABEL: f41 +; CHECK: risbg %r2, %r2, 36, 191, 62 +; CHECK: br %r14 + %shl = shl i32 %a, 2 + %shr = lshr i32 %shl, 4 + %ext = zext i32 %shr to i64 + ret i64 %ext +} + ; In this case the sign extension is converted to a pair of 32-bit shifts, ; which is then extended to 64 bits. We previously used the wrong bit size ; when testing whether the shifted-in bits of the shift right were significant. -define i64 @f41(i1 %x) { -; CHECK-LABEL: f41: +define i64 @f42(i1 %x) { +; CHECK-LABEL: f42: ; CHECK: sll %r2, 31 ; CHECK: sra %r2, 31 ; CHECK: llgcr %r2, %r2 |
