diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrArithmetic.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/MergeConsecutiveStores.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/copy-eflags.ll | 18 |
4 files changed, 19 insertions, 18 deletions
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index f0b42a29591..f59afc67ccb 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -435,11 +435,10 @@ def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), // TODO: inc/dec is slow for P4, but fast for Pentium-M. let Defs = [EFLAGS] in { let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { -let CodeSize = 2 in +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), "inc{b}\t$dst", [(set GR8:$dst, EFLAGS, (X86add_flag_nocf GR8:$src1, 1))]>; -let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. def INC16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), "inc{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86add_flag_nocf GR16:$src1, 1))]>, @@ -483,11 +482,10 @@ let Predicates = [UseIncDec, In64BitMode] in { } // CodeSize = 2, SchedRW let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { -let CodeSize = 2 in +let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), "dec{b}\t$dst", [(set GR8:$dst, EFLAGS, (X86sub_flag_nocf GR8:$src1, 1))]>; -let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), "dec{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86sub_flag_nocf GR16:$src1, 1))]>, diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index f17d8812a8a..01b17404d3c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -761,9 +761,11 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA( .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0); break; } + case X86::INC8r: case X86::INC16r: addRegOffset(MIB, InRegLEA, true, 1); break; + case X86::DEC8r: case X86::DEC16r: addRegOffset(MIB, InRegLEA, true, -1); break; @@ -945,8 +947,6 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, NewMI = addOffset(MIB, 1); break; } - case X86::INC16r: - return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); case X86::DEC64r: case X86::DEC32r: { assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!"); @@ -970,7 +970,12 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, break; } + case X86::DEC8r: + case X86::INC8r: + Is8BitOp = true; + LLVM_FALLTHROUGH; case X86::DEC16r: + case X86::INC16r: return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); case X86::ADD64rr: case X86::ADD64rr_DB: diff --git a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll index 4f457888dbc..edec3fdd7f5 100644 --- a/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll +++ b/llvm/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -632,7 +632,7 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { ; BWON-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; BWON-NEXT: movsbq (%rdi,%rcx), %rax ; BWON-NEXT: movzbl (%rdx,%rax), %r9d -; BWON-NEXT: incb %al +; BWON-NEXT: leal 1(%rax), %eax ; BWON-NEXT: movsbq %al, %rax ; BWON-NEXT: movzbl (%rdx,%rax), %eax ; BWON-NEXT: movb %r9b, (%rsi,%rcx,2) @@ -651,7 +651,7 @@ define void @loadStoreBaseIndexOffsetSextNoSex(i8* %a, i8* %b, i8* %c, i32 %n) { ; BWOFF-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; BWOFF-NEXT: movsbq (%rdi,%rcx), %rax ; BWOFF-NEXT: movb (%rdx,%rax), %r9b -; BWOFF-NEXT: incb %al +; BWOFF-NEXT: leal 1(%rax), %eax ; BWOFF-NEXT: movsbq %al, %rax ; BWOFF-NEXT: movb (%rdx,%rax), %al ; BWOFF-NEXT: movb %r9b, (%rsi,%rcx,2) diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll index 018ea8bbee2..20969c93e93 100644 --- a/llvm/test/CodeGen/X86/copy-eflags.ll +++ b/llvm/test/CodeGen/X86/copy-eflags.ll @@ -43,19 +43,17 @@ define i32 @test1() nounwind { ; ; X64-LABEL: test1: ; X64: # %bb.0: # %entry -; X64-NEXT: movb {{.*}}(%rip), %dil -; X64-NEXT: movl %edi, %eax -; X64-NEXT: incb %al +; X64-NEXT: movb {{.*}}(%rip), %cl +; X64-NEXT: leal 1(%rcx), %eax ; X64-NEXT: movb %al, {{.*}}(%rip) ; X64-NEXT: incl {{.*}}(%rip) -; X64-NEXT: sete %sil -; X64-NEXT: movb {{.*}}(%rip), %cl -; X64-NEXT: movl %ecx, %edx -; X64-NEXT: incb %dl -; X64-NEXT: cmpb %dil, %cl +; X64-NEXT: sete %dl +; X64-NEXT: movb {{.*}}(%rip), %sil +; X64-NEXT: leal 1(%rsi), %edi +; X64-NEXT: cmpb %cl, %sil ; X64-NEXT: sete {{.*}}(%rip) -; X64-NEXT: movb %dl, {{.*}}(%rip) -; X64-NEXT: testb %sil, %sil +; X64-NEXT: movb %dil, {{.*}}(%rip) +; X64-NEXT: testb %dl, %dl ; X64-NEXT: jne .LBB0_2 ; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: pushq %rax |
