diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 62 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 342 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterInfo.td | 27 | ||||
| -rw-r--r-- | llvm/test/MC/AArch64/basic-a64-diagnostics.s | 95 |
4 files changed, 320 insertions, 206 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 777200281d8..7800b62e9fe 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -2684,7 +2684,7 @@ class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops, let DecoderMethod = "DecodeUnsignedLdStInstruction"; } -multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, Operand indextype, string asm, list<dag> pattern> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt), @@ -2696,7 +2696,7 @@ multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>; } -multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, Operand indextype, string asm, list<dag> pattern> { let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def ui : BaseLoadStoreUI<sz, V, opc, (outs), @@ -2756,7 +2756,7 @@ def am_ldrlit : Operand<iPTR> { } let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in -class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm> +class LoadLiteral<bits<2> opc, bit V, RegisterOperand regtype, string asm> : I<(outs regtype:$Rt), (ins am_ldrlit:$label), asm, "\t$Rt, $label", "", []>, Sched<[WriteLD]> { @@ -2867,7 +2867,7 @@ def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>; def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128, ro_Xextend128>; -class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list<dag> pat> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> { bits<5> Rt; @@ -2889,11 +2889,11 @@ class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, let Inst{4-0} = Rt; } -class ROInstAlias<string asm, RegisterClass regtype, Instruction INST> +class ROInstAlias<string asm, RegisterOperand regtype, Instruction INST> : InstAlias<asm # "\t$Rt, [$Rn, $Rm]", (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>; -multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore8RO<sz, V, opc, regtype, asm, @@ -2920,7 +2920,7 @@ multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs), @@ -2945,7 +2945,7 @@ multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list<dag> pat> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> { bits<5> Rt; @@ -2967,7 +2967,7 @@ class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, let Inst{4-0} = Rt; } -multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt), @@ -2992,7 +2992,7 @@ multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs), @@ -3017,7 +3017,7 @@ multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list<dag> pat> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> { bits<5> Rt; @@ -3039,7 +3039,7 @@ class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, let Inst{4-0} = Rt; } -multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10 in def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt), @@ -3064,7 +3064,7 @@ multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10 in def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs), @@ -3089,7 +3089,7 @@ multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list<dag> pat> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> { bits<5> Rt; @@ -3111,7 +3111,7 @@ class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, let Inst{4-0} = Rt; } -multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt), @@ -3136,7 +3136,7 @@ multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs), @@ -3161,7 +3161,7 @@ multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, dag ins, dag outs, list<dag> pat> : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> { bits<5> Rt; @@ -3183,7 +3183,7 @@ class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, let Inst{4-0} = Rt; } -multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator loadop> { let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt), @@ -3208,7 +3208,7 @@ multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>; } -multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, ValueType Ty, SDPatternOperator storeop> { let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs), @@ -3322,7 +3322,7 @@ class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops, let DecoderMethod = "DecodeSignedLdStInstruction"; } -multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, list<dag> pattern> { let AddedComplexity = 1 in // try this before LoadUI def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt), @@ -3333,7 +3333,7 @@ multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; } -multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, list<dag> pattern> { let AddedComplexity = 1 in // try this before StoreUI def i : BaseLoadStoreUnscale<sz, V, opc, (outs), @@ -3430,7 +3430,7 @@ class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops, let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in -class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm> : BaseLoadStorePreIdx<sz, V, opc, (outs GPR64sp:$wback, regtype:$Rt), @@ -3439,7 +3439,7 @@ class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, Sched<[WriteLD, WriteAdr]>; let mayStore = 1, mayLoad = 0 in -class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, SDPatternOperator storeop, ValueType Ty> : BaseLoadStorePreIdx<sz, V, opc, (outs GPR64sp:$wback), @@ -3476,7 +3476,7 @@ class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops, let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in -class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm> : BaseLoadStorePostIdx<sz, V, opc, (outs GPR64sp:$wback, regtype:$Rt), @@ -3485,7 +3485,7 @@ class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, Sched<[WriteLD, WriteAdr]>; let mayStore = 1, mayLoad = 0 in -class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype, +class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterOperand regtype, string asm, SDPatternOperator storeop, ValueType Ty> : BaseLoadStorePostIdx<sz, V, opc, (outs GPR64sp:$wback), @@ -3523,7 +3523,7 @@ class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops, let DecoderMethod = "DecodePairLdStInstruction"; } -multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype, +multiclass LoadPairOffset<bits<2> opc, bit V, RegisterOperand regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in def i : BaseLoadStorePairOffset<opc, V, 1, @@ -3537,7 +3537,7 @@ multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype, } -multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype, +multiclass StorePairOffset<bits<2> opc, bit V, RegisterOperand regtype, Operand indextype, string asm> { let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in def i : BaseLoadStorePairOffset<opc, V, 0, (outs), @@ -3574,7 +3574,7 @@ class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops, let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in -class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype, +class LoadPairPreIdx<bits<2> opc, bit V, RegisterOperand regtype, Operand indextype, string asm> : BaseLoadStorePairPreIdx<opc, V, 1, (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2), @@ -3582,7 +3582,7 @@ class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype, Sched<[WriteLD, WriteLDHi, WriteAdr]>; let mayStore = 1, mayLoad = 0 in -class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype, +class StorePairPreIdx<bits<2> opc, bit V, RegisterOperand regtype, Operand indextype, string asm> : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback), (ins regtype:$Rt, regtype:$Rt2, @@ -3615,7 +3615,7 @@ class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops, let hasSideEffects = 0 in { let mayStore = 0, mayLoad = 1 in -class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype, +class LoadPairPostIdx<bits<2> opc, bit V, RegisterOperand regtype, Operand idxtype, string asm> : BaseLoadStorePairPostIdx<opc, V, 1, (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2), @@ -3623,7 +3623,7 @@ class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype, Sched<[WriteLD, WriteLDHi, WriteAdr]>; let mayStore = 1, mayLoad = 0 in -class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype, +class StorePairPostIdx<bits<2> opc, bit V, RegisterOperand regtype, Operand idxtype, string asm> : BaseLoadStorePairPostIdx<opc, V, 0, (outs GPR64sp:$wback), (ins regtype:$Rt, regtype:$Rt2, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 273fd0a7fd9..ba89677424c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1439,39 +1439,39 @@ def : InstAlias<"dcps3", (DCPS3 0)>; //===----------------------------------------------------------------------===// // Pair (indexed, offset) -defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">; -defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">; -defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">; -defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">; -defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">; +defm LDPW : LoadPairOffset<0b00, 0, GPR32z, simm7s4, "ldp">; +defm LDPX : LoadPairOffset<0b10, 0, GPR64z, simm7s8, "ldp">; +defm LDPS : LoadPairOffset<0b00, 1, FPR32Op, simm7s4, "ldp">; +defm LDPD : LoadPairOffset<0b01, 1, FPR64Op, simm7s8, "ldp">; +defm LDPQ : LoadPairOffset<0b10, 1, FPR128Op, simm7s16, "ldp">; -defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">; +defm LDPSW : LoadPairOffset<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (pre-indexed) -def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">; -def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">; -def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">; -def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">; -def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">; +def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32z, simm7s4, "ldp">; +def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64z, simm7s8, "ldp">; +def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; +def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; +def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; -def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">; +def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (post-indexed) -def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">; -def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">; -def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">; -def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">; -def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">; +def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32z, simm7s4, "ldp">; +def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64z, simm7s8, "ldp">; +def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32Op, simm7s4, "ldp">; +def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64Op, simm7s8, "ldp">; +def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128Op, simm7s16, "ldp">; -def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">; +def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64z, simm7s4, "ldpsw">; // Pair (no allocate) -defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">; -defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">; -defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">; -defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">; -defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">; +defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32z, simm7s4, "ldnp">; +defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64z, simm7s8, "ldnp">; +defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32Op, simm7s4, "ldnp">; +defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64Op, simm7s8, "ldnp">; +defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128Op, simm7s16, "ldnp">; //--- // (register offset) @@ -1484,11 +1484,11 @@ defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>; defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>; // Floating-point -defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>; -defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>; -defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>; -defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>; -defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>; +defm LDRB : Load8RO<0b00, 1, 0b01, FPR8Op, "ldr", untyped, load>; +defm LDRH : Load16RO<0b01, 1, 0b01, FPR16Op, "ldr", f16, load>; +defm LDRS : Load32RO<0b10, 1, 0b01, FPR32Op, "ldr", f32, load>; +defm LDRD : Load64RO<0b11, 1, 0b01, FPR64Op, "ldr", f64, load>; +defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128Op, "ldr", f128, load>; // Load sign-extended half-word defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>; @@ -1650,26 +1650,26 @@ let AddedComplexity = 10 in { //--- // (unsigned immediate) //--- -defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr", - [(set GPR64:$Rt, +defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr", + [(set GPR64z:$Rt, (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; -defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr", - [(set GPR32:$Rt, +defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr", + [(set GPR32z:$Rt, (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; -defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr", - [(set FPR8:$Rt, +defm LDRB : LoadUI<0b00, 1, 0b01, FPR8Op, uimm12s1, "ldr", + [(set FPR8Op:$Rt, (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>; -defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr", - [(set (f16 FPR16:$Rt), +defm LDRH : LoadUI<0b01, 1, 0b01, FPR16Op, uimm12s2, "ldr", + [(set (f16 FPR16Op:$Rt), (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>; -defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr", - [(set (f32 FPR32:$Rt), +defm LDRS : LoadUI<0b10, 1, 0b01, FPR32Op, uimm12s4, "ldr", + [(set (f32 FPR32Op:$Rt), (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>; -defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr", - [(set (f64 FPR64:$Rt), +defm LDRD : LoadUI<0b11, 1, 0b01, FPR64Op, uimm12s8, "ldr", + [(set (f64 FPR64Op:$Rt), (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>; -defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr", - [(set (f128 FPR128:$Rt), +defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128Op, uimm12s16, "ldr", + [(set (f128 FPR128Op:$Rt), (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>; // For regular load, we do not have any alignment requirement. @@ -1824,14 +1824,14 @@ def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>; //--- // (literal) -def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">; -def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">; -def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">; -def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">; -def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">; +def LDRWl : LoadLiteral<0b00, 0, GPR32z, "ldr">; +def LDRXl : LoadLiteral<0b01, 0, GPR64z, "ldr">; +def LDRSl : LoadLiteral<0b00, 1, FPR32Op, "ldr">; +def LDRDl : LoadLiteral<0b01, 1, FPR64Op, "ldr">; +def LDRQl : LoadLiteral<0b10, 1, FPR128Op, "ldr">; // load sign-extended word -def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">; +def LDRSWl : LoadLiteral<0b10, 0, GPR64z, "ldrsw">; // prefetch def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; @@ -1839,26 +1839,26 @@ def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>; //--- // (unscaled immediate) -defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur", - [(set GPR64:$Rt, +defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64z, "ldur", + [(set GPR64z:$Rt, (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur", - [(set GPR32:$Rt, +defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32z, "ldur", + [(set GPR32z:$Rt, (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur", - [(set FPR8:$Rt, +defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8Op, "ldur", + [(set FPR8Op:$Rt, (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur", - [(set FPR16:$Rt, +defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16Op, "ldur", + [(set FPR16Op:$Rt, (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur", - [(set (f32 FPR32:$Rt), +defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32Op, "ldur", + [(set (f32 FPR32Op:$Rt), (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur", - [(set (f64 FPR64:$Rt), +defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64Op, "ldur", + [(set (f64 FPR64Op:$Rt), (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>; -defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur", - [(set (f128 FPR128:$Rt), +defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128Op, "ldur", + [(set (f128 FPR128Op:$Rt), (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>; defm LDURHH @@ -1978,15 +1978,15 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", - (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; + (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", - (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; + (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", - (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; + (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", - (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; + (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", - (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; + (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), @@ -2062,53 +2062,53 @@ defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">; //--- // (immediate pre-indexed) -def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">; -def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">; -def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">; -def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">; -def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">; -def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">; -def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">; +def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32z, "ldr">; +def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64z, "ldr">; +def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8Op, "ldr">; +def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16Op, "ldr">; +def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32Op, "ldr">; +def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64Op, "ldr">; +def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128Op, "ldr">; // load sign-extended half-word -def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">; -def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">; +def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; +def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; // load sign-extended byte -def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">; -def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">; +def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; +def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; // load zero-extended byte -def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">; -def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">; +def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32z, "ldrb">; +def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32z, "ldrh">; // load sign-extended word -def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">; +def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; //--- // (immediate post-indexed) -def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">; -def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">; -def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">; -def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">; -def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">; -def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">; -def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">; +def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32z, "ldr">; +def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">; +def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8Op, "ldr">; +def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16Op, "ldr">; +def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32Op, "ldr">; +def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64Op, "ldr">; +def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128Op, "ldr">; // load sign-extended half-word -def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">; -def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">; +def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32z, "ldrsh">; +def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64z, "ldrsh">; // load sign-extended byte -def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">; -def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">; +def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32z, "ldrsb">; +def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64z, "ldrsb">; // load zero-extended byte -def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">; -def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">; +def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32z, "ldrb">; +def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">; // load sign-extended word -def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">; +def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">; //===----------------------------------------------------------------------===// // Store instructions. @@ -2116,32 +2116,32 @@ def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">; // Pair (indexed, offset) // FIXME: Use dedicated range-checked addressing mode operand here. -defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">; -defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">; -defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">; -defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">; -defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">; +defm STPW : StorePairOffset<0b00, 0, GPR32z, simm7s4, "stp">; +defm STPX : StorePairOffset<0b10, 0, GPR64z, simm7s8, "stp">; +defm STPS : StorePairOffset<0b00, 1, FPR32Op, simm7s4, "stp">; +defm STPD : StorePairOffset<0b01, 1, FPR64Op, simm7s8, "stp">; +defm STPQ : StorePairOffset<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (pre-indexed) -def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">; -def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">; -def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">; -def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">; -def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">; +def STPWpre : StorePairPreIdx<0b00, 0, GPR32z, simm7s4, "stp">; +def STPXpre : StorePairPreIdx<0b10, 0, GPR64z, simm7s8, "stp">; +def STPSpre : StorePairPreIdx<0b00, 1, FPR32Op, simm7s4, "stp">; +def STPDpre : StorePairPreIdx<0b01, 1, FPR64Op, simm7s8, "stp">; +def STPQpre : StorePairPreIdx<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (pre-indexed) -def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">; -def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">; -def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">; -def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">; -def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">; +def STPWpost : StorePairPostIdx<0b00, 0, GPR32z, simm7s4, "stp">; +def STPXpost : StorePairPostIdx<0b10, 0, GPR64z, simm7s8, "stp">; +def STPSpost : StorePairPostIdx<0b00, 1, FPR32Op, simm7s4, "stp">; +def STPDpost : StorePairPostIdx<0b01, 1, FPR64Op, simm7s8, "stp">; +def STPQpost : StorePairPostIdx<0b10, 1, FPR128Op, simm7s16, "stp">; // Pair (no allocate) -defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">; -defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">; -defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">; -defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">; -defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">; +defm STNPW : StorePairNoAlloc<0b00, 0, GPR32z, simm7s4, "stnp">; +defm STNPX : StorePairNoAlloc<0b10, 0, GPR64z, simm7s8, "stnp">; +defm STNPS : StorePairNoAlloc<0b00, 1, FPR32Op, simm7s4, "stnp">; +defm STNPD : StorePairNoAlloc<0b01, 1, FPR64Op, simm7s8, "stnp">; +defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128Op, simm7s16, "stnp">; //--- // (Register offset) @@ -2154,11 +2154,11 @@ defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>; // Floating-point -defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>; -defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>; -defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>; -defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>; -defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>; +defm STRB : Store8RO< 0b00, 1, 0b00, FPR8Op, "str", untyped, store>; +defm STRH : Store16RO<0b01, 1, 0b00, FPR16Op, "str", f16, store>; +defm STRS : Store32RO<0b10, 1, 0b00, FPR32Op, "str", f32, store>; +defm STRD : Store64RO<0b11, 1, 0b00, FPR64Op, "str", f64, store>; +defm STRQ : Store128RO<0b00, 1, 0b10, FPR128Op, "str", f128, store>; let Predicates = [UseSTRQro], AddedComplexity = 10 in { def : Pat<(store (f128 FPR128:$Rt), @@ -2265,19 +2265,19 @@ defm STRX : StoreUIz<0b11, 0, 0b00, GPR64z, uimm12s8, "str", defm STRW : StoreUIz<0b10, 0, 0b00, GPR32z, uimm12s4, "str", [(store GPR32z:$Rt, (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; -defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str", - [(store FPR8:$Rt, +defm STRB : StoreUI<0b00, 1, 0b00, FPR8Op, uimm12s1, "str", + [(store FPR8Op:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>; -defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str", - [(store (f16 FPR16:$Rt), +defm STRH : StoreUI<0b01, 1, 0b00, FPR16Op, uimm12s2, "str", + [(store (f16 FPR16Op:$Rt), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>; -defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str", - [(store (f32 FPR32:$Rt), +defm STRS : StoreUI<0b10, 1, 0b00, FPR32Op, uimm12s4, "str", + [(store (f32 FPR32Op:$Rt), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>; -defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str", - [(store (f64 FPR64:$Rt), +defm STRD : StoreUI<0b11, 1, 0b00, FPR64Op, uimm12s8, "str", + [(store (f64 FPR64Op:$Rt), (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>; -defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>; +defm STRQ : StoreUI<0b00, 1, 0b10, FPR128Op, uimm12s16, "str", []>; defm STRHH : StoreUIz<0b01, 0, 0b00, GPR32z, uimm12s2, "strh", [(truncstorei16 GPR32z:$Rt, @@ -2358,32 +2358,32 @@ def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)), //--- // (unscaled immediate) -defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur", - [(store GPR64:$Rt, +defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64z, "stur", + [(store GPR64z:$Rt, (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; -defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur", - [(store GPR32:$Rt, +defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32z, "stur", + [(store GPR32z:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; -defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur", - [(store FPR8:$Rt, +defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8Op, "stur", + [(store FPR8Op:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; -defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur", - [(store (f16 FPR16:$Rt), +defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16Op, "stur", + [(store (f16 FPR16Op:$Rt), (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; -defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur", - [(store (f32 FPR32:$Rt), +defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32Op, "stur", + [(store (f32 FPR32Op:$Rt), (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>; -defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur", - [(store (f64 FPR64:$Rt), +defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64Op, "stur", + [(store (f64 FPR64Op:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>; -defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur", - [(store (f128 FPR128:$Rt), +defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128Op, "stur", + [(store (f128 FPR128Op:$Rt), (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>; -defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh", - [(truncstorei16 GPR32:$Rt, +defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32z, "sturh", + [(truncstorei16 GPR32z:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>; -defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb", - [(truncstorei8 GPR32:$Rt, +defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb", + [(truncstorei8 GPR32z:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>; // Match all store 64 bits width whose type is compatible with FPR64 @@ -2454,15 +2454,15 @@ def : InstAlias<"str $Rt, [$Rn, $offset]", def : InstAlias<"str $Rt, [$Rn, $offset]", (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", - (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; + (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", - (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; + (STURHi FPR16Op:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", - (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; + (STURSi FPR32Op:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", - (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; + (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", - (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; + (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; def : InstAlias<"strb $Rt, [$Rn, $offset]", (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; @@ -2479,16 +2479,16 @@ defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">; //--- // (immediate pre-indexed) -def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>; -def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>; -def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>; -def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>; -def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>; -def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>; -def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>; +def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32z, "str", pre_store, i32>; +def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64z, "str", pre_store, i64>; +def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8Op, "str", pre_store, untyped>; +def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16Op, "str", pre_store, f16>; +def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32Op, "str", pre_store, f32>; +def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64Op, "str", pre_store, f64>; +def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128Op, "str", pre_store, f128>; -def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>; -def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>; +def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32z, "strb", pre_truncsti8, i32>; +def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32z, "strh", pre_truncsti16, i32>; // truncstore i64 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), @@ -2533,16 +2533,16 @@ def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), //--- // (immediate post-indexed) -def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>; -def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>; -def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>; -def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>; -def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>; -def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>; -def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>; - -def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>; -def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>; +def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32z, "str", post_store, i32>; +def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64z, "str", post_store, i64>; +def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8Op, "str", post_store, untyped>; +def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16Op, "str", post_store, f16>; +def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32Op, "str", post_store, f32>; +def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64Op, "str", post_store, f64>; +def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128Op, "str", post_store, f128>; + +def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32z, "strb", post_truncsti8, i32>; +def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32z, "strh", post_truncsti16, i32>; // truncstore i64 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off), diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index 557e75926a4..b150d55e9e2 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -612,13 +612,32 @@ defm VecListTwo : VectorList<2, DD, QQ>; defm VecListThree : VectorList<3, DDD, QQQ>; defm VecListFour : VectorList<4, DDDD, QQQQ>; +class FPRAsmOperand<string RC> : AsmOperandClass { + let Name = "FPRAsmOperand" # RC; + let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>"; + let RenderMethod = "addRegOperands"; +} // Register operand versions of the scalar FP registers. -def FPR16Op : RegisterOperand<FPR16, "printOperand">; -def FPR32Op : RegisterOperand<FPR32, "printOperand">; -def FPR64Op : RegisterOperand<FPR64, "printOperand">; -def FPR128Op : RegisterOperand<FPR128, "printOperand">; +def FPR8Op : RegisterOperand<FPR8, "printOperand"> { + let ParserMatchClass = FPRAsmOperand<"FPR8">; +} + +def FPR16Op : RegisterOperand<FPR16, "printOperand"> { + let ParserMatchClass = FPRAsmOperand<"FPR16">; +} +def FPR32Op : RegisterOperand<FPR32, "printOperand"> { + let ParserMatchClass = FPRAsmOperand<"FPR32">; +} + +def FPR64Op : RegisterOperand<FPR64, "printOperand"> { + let ParserMatchClass = FPRAsmOperand<"FPR64">; +} + +def FPR128Op : RegisterOperand<FPR128, "printOperand"> { + let ParserMatchClass = FPRAsmOperand<"FPR128">; +} //===----------------------------------------------------------------------===// // ARMv8.1a atomic CASP register operands diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s index 3b791bef0b6..d5467e613e5 100644 --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -1851,12 +1851,16 @@ ldr sp, some_label ldrsw w3, somewhere + ldr v0, some_label // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr sp, some_label // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsw w3, somewhere // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, some_label +// CHECK-ERROR-NEXT: ^ ldrsw x2, #1048576 ldr q0, #-1048580 @@ -1913,6 +1917,14 @@ //------------------------------------------------------------------------------ // Load/store (unscaled immediate) //------------------------------------------------------------------------------ + ldur v0, [x0, #0] + stur v0, [x0, #0] +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldur v0, [x0, #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: stur v0, [x0, #0] +// CHECK-ERROR-NEXT: ^ ldurb w2, [sp, #256] sturh w17, [x1, #256] @@ -1960,6 +1972,15 @@ //------------------------------------------------------------------------------ // Load-store register (immediate post-indexed) //------------------------------------------------------------------------------ + ldr v0, [x0], #0 + str v0, [x0], #0 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0], #0 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0], #0 +// CHECK-ERROR-NEXT: ^ + ldr x3, [x4, #25], #0 ldr x4, [x9, #0], #4 // CHECK-ERROR-AARCH64: error: invalid operand for instruction @@ -2147,6 +2168,14 @@ //------------------------------------------------------------------------------ // Load-store register (immediate pre-indexed) //------------------------------------------------------------------------------ + ldr v0, [x0, #0]! + str v0, [x0, #0]! +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0, #0]! +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0, #0]! +// CHECK-ERROR-NEXT: ^ ldr x3, [x4]! // CHECK-ERROR: error: @@ -2357,6 +2386,14 @@ //------------------------------------------------------------------------------ // Load/store (unsigned immediate) //------------------------------------------------------------------------------ + ldr v0, [x0, #0] + str v0, [x0, #0] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0, #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0, #0] +// CHECK-ERROR-NEXT: ^ //// Out of range immediates ldr q0, [x11, #65536] @@ -2446,6 +2483,30 @@ //------------------------------------------------------------------------------ // Load/store register (register offset) //------------------------------------------------------------------------------ + ldr v0, [x0, xzr] + ldr v0, [x0, x1, lsl #0] + ldr v0, [x0, x1, lsl #0] + str v0, [x0, xzr] + str v0, [x0, x1, lsl #0] + str v0, [x0, x1, lsl #0] +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0, xzr] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0, x1, lsl #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldr v0, [x0, x1, lsl #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0, xzr] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0, x1, lsl #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: str v0, [x0, x1, lsl #0] +// CHECK-ERROR-NEXT: ^ ldr w3, [xzr, x3] ldr w4, [x0, x4, lsl] @@ -2534,6 +2595,15 @@ //------------------------------------------------------------------------------ // Load/store register pair (offset) //------------------------------------------------------------------------------ + ldp v0, v1, [x0, #0] + stp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: stp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: ^ + ldp w3, w2, [x4, #1] stp w1, w2, [x3, #253] stp w9, w10, [x5, #256] @@ -2636,6 +2706,14 @@ //------------------------------------------------------------------------------ // Load/store register pair (post-indexed) //------------------------------------------------------------------------------ + ldp v0, v1, [x0], #0 + stp v0, v1, [x0], #0 +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldp v0, v1, [x0], #0 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: stp v0, v1, [x0], #0 +// CHECK-ERROR-NEXT: ^ ldp w3, w2, [x4], #1 stp w1, w2, [x3], #253 @@ -2739,6 +2817,14 @@ //------------------------------------------------------------------------------ // Load/store register pair (pre-indexed) //------------------------------------------------------------------------------ + ldp v0, v1, [x0, #0]! + stp v0, v1, [x0, #0]! +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldp v0, v1, [x0, #0]! +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: stp v0, v1, [x0, #0]! +// CHECK-ERROR-NEXT: ^ ldp w3, w2, [x4, #1]! stp w1, w2, [x3, #253]! @@ -2842,6 +2928,15 @@ //------------------------------------------------------------------------------ // Load/store register pair (offset) //------------------------------------------------------------------------------ + ldnp v0, v1, [x0, #0] + stnp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: ldnp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: stnp v0, v1, [x0, #0] +// CHECK-ERROR-NEXT: ^ + ldnp w3, w2, [x4, #1] stnp w1, w2, [x3, #253] stnp w9, w10, [x5, #256] |
