diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-double-precision-shift-left.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-64-double-precision-shift-right.ll | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/x86-64-double-precision-shift-left.ll b/llvm/test/CodeGen/X86/x86-64-double-precision-shift-left.ll index 75e9052c129..7515c46f7ce 100644 --- a/llvm/test/CodeGen/X86/x86-64-double-precision-shift-left.ll +++ b/llvm/test/CodeGen/X86/x86-64-double-precision-shift-left.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s ; Verify that for the architectures that are known to have poor latency ; double precision shift instructions we generate alternative sequence ; of instructions with lower latencies instead of shld instruction. diff --git a/llvm/test/CodeGen/X86/x86-64-double-precision-shift-right.ll b/llvm/test/CodeGen/X86/x86-64-double-precision-shift-right.ll index bc2f39ee666..5e3f2294171 100644 --- a/llvm/test/CodeGen/X86/x86-64-double-precision-shift-right.ll +++ b/llvm/test/CodeGen/X86/x86-64-double-precision-shift-right.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s ; Verify that for the architectures that are known to have poor latency ; double precision shift instructions we generate alternative sequence ; of instructions with lower latencies instead of shrd instruction. |
