diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFastISel.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr26180.ll | 14 |
4 files changed, 20 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp index 3980ecfac77..1de26790651 100644 --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -1068,10 +1068,10 @@ unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, if (!PPCEmitStore(MVT::f64, SrcReg, Addr)) return 0; - // Reload it into a GPR. If we want an i32, modify the address - // to have a 4-byte offset so we load from the right place. + // Reload it into a GPR. If we want an i32 on big endian, modify the + // address to have a 4-byte offset so we load from the right place. if (VT == MVT::i32) - Addr.Offset = 4; + Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4; // Look at the currently assigned register for this instruction // to determine the required register class. diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 59086f1cbb9..3fe7cf3cbf5 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -6163,11 +6163,11 @@ void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, MPI, false, false, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to - // add in a bias. + // add in a bias on big endian. if (Op.getValueType() == MVT::i32 && !i32Stack) { FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, dl, FIPtr.getValueType())); - MPI = MPI.getWithOffset(4); + MPI = MPI.getWithOffset(Subtarget.isLittleEndian() ? 0 : 4); } RLI.Chain = Chain; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index c357c7564d7..359c2eb85b3 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -110,7 +110,7 @@ void PPCSubtarget::initializeEnvironment() { void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { // Determine default and user specified characteristics std::string CPUName = CPU; - if (CPUName.empty()) { + if (CPUName.empty() || CPU == "generic") { // If cross-compiling with -march=ppc64le without -mcpu if (TargetTriple.getArch() == Triple::ppc64le) CPUName = "ppc64le"; diff --git a/llvm/test/CodeGen/PowerPC/pr26180.ll b/llvm/test/CodeGen/PowerPC/pr26180.ll new file mode 100644 index 00000000000..e4cbcb8725d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr26180.ll @@ -0,0 +1,14 @@ +; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s --check-prefix=GENERIC +; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s + +define i32 @bad(double %x) { + %1 = fptoui double %x to i32 + ret i32 %1 +} + +; CHECK: fctidz 1, 1 +; CHECK: stfd 1, [[OFF:.*]](1) +; CHECK: lwz {{[0-9]*}}, [[OFF]](1) +; GENERIC: fctiwuz 1, 1 +; GENERIC: stfd 1, [[OFF:.*]](1) +; GENERIC: lwz {{[0-9]*}}, [[OFF]](1) |
