diff options
| -rw-r--r-- | llvm/test/CodeGen/X86/signbit-shift.ll | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll index 743664fd506..e631da8f39c 100644 --- a/llvm/test/CodeGen/X86/signbit-shift.ll +++ b/llvm/test/CodeGen/X86/signbit-shift.ll @@ -29,6 +29,20 @@ define i32 @add_zext_ifpos(i32 %x) { ret i32 %r } +define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) { +; CHECK-LABEL: add_zext_ifpos_vec_splat: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 +; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 +; CHECK-NEXT: psrld $31, %xmm0 +; CHECK-NEXT: por {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + %e = zext <4 x i1> %c to <4 x i32> + %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> + ret <4 x i32> %r +} + define i32 @sel_ifpos_tval_bigger(i32 %x) { ; CHECK-LABEL: sel_ifpos_tval_bigger: ; CHECK: # %bb.0: @@ -68,6 +82,19 @@ define i32 @add_sext_ifpos(i32 %x) { ret i32 %r } +define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) { +; CHECK-LABEL: add_sext_ifpos_vec_splat: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 +; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 +; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + %e = sext <4 x i1> %c to <4 x i32> + %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> + ret <4 x i32> %r +} + define i32 @sel_ifpos_fval_bigger(i32 %x) { ; CHECK-LABEL: sel_ifpos_fval_bigger: ; CHECK: # %bb.0: @@ -155,3 +182,60 @@ define i32 @sel_ifneg_fval_bigger(i32 %x) { ret i32 %r } +define i32 @add_lshr_not(i32 %x) { +; CHECK-LABEL: add_lshr_not: +; CHECK: # %bb.0: +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: notl %edi +; CHECK-NEXT: shrl $31, %edi +; CHECK-NEXT: leal 41(%rdi), %eax +; CHECK-NEXT: retq + %not = xor i32 %x, -1 + %sh = lshr i32 %not, 31 + %r = add i32 %sh, 41 + ret i32 %r +} + +define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) { +; CHECK-LABEL: add_lshr_not_vec_splat: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 +; CHECK-NEXT: pxor %xmm1, %xmm0 +; CHECK-NEXT: psrld $31, %xmm0 +; CHECK-NEXT: por {{.*}}(%rip), %xmm0 +; CHECK-NEXT: retq + %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> + %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> + ret <4 x i32> %r +} + +define i32 @sub_lshr_not(i32 %x) { +; CHECK-LABEL: sub_lshr_not: +; CHECK: # %bb.0: +; CHECK-NEXT: notl %edi +; CHECK-NEXT: shrl $31, %edi +; CHECK-NEXT: xorl $43, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + %not = xor i32 %x, -1 + %sh = lshr i32 %not, 31 + %r = sub i32 43, %sh + ret i32 %r +} + +define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { +; CHECK-LABEL: sub_lshr_not_vec_splat: +; CHECK: # %bb.0: +; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 +; CHECK-NEXT: pxor %xmm0, %xmm1 +; CHECK-NEXT: psrld $31, %xmm1 +; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [42,42,42,42] +; CHECK-NEXT: psubd %xmm1, %xmm0 +; CHECK-NEXT: retq + %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> + %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> + %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e + ret <4 x i32> %r +} + |
