diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/vdiv_combine.ll | 8 |
2 files changed, 12 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 6f886220bd2..cafb4500d1a 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -9908,10 +9908,12 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, uint32_t FloatBits = FloatTy.getSizeInBits(); MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType(); uint32_t IntBits = IntTy.getSizeInBits(); - if (FloatBits != 32 || IntBits > 32) { + unsigned NumLanes = Op.getValueType().getVectorNumElements(); + if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { // These instructions only exist converting from i32 to f32. We can handle // smaller integers by generating an extra extend, but larger ones would - // be lossy. + // be lossy. We also can't handle more then 4 lanes, since these intructions + // only support v2i32/v4i32 types. return SDValue(); } @@ -9922,7 +9924,6 @@ static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG, SDLoc dl(N); SDValue ConvInput = Op.getOperand(0); - unsigned NumLanes = Op.getValueType().getVectorNumElements(); if (IntBits < FloatBits) ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, diff --git a/llvm/test/CodeGen/ARM/vdiv_combine.ll b/llvm/test/CodeGen/ARM/vdiv_combine.ll index 8c6e4ba3505..dbbf92efd22 100644 --- a/llvm/test/CodeGen/ARM/vdiv_combine.ll +++ b/llvm/test/CodeGen/ARM/vdiv_combine.ll @@ -136,3 +136,11 @@ define <2 x double> @fix_i64_to_double(<2 x i64> %in) { ret <2 x double> %shift } +; Don't combine with 8 lanes. Just make sure things don't crash. +; CHECK-LABEL: test7 +define <8 x float> @test7(<8 x i32> %in) nounwind { +entry: + %vcvt.i = sitofp <8 x i32> %in to <8 x float> + %div.i = fdiv <8 x float> %vcvt.i, <float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0> + ret <8 x float> %div.i +} |
