diff options
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/store-vector-ptrs.ll | 8 |
3 files changed, 12 insertions, 12 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp index a624b701bc0..ee7d217b7b8 100644 --- a/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp @@ -869,14 +869,19 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc, const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); MachineRegisterInfo &MRI = MF.getRegInfo(); - + const SITargetLowering& Lowering = + *static_cast<const SITargetLowering*>(getTargetLowering()); unsigned ScratchPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR); unsigned ScratchOffsetReg = TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET); + Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass, + ScratchOffsetReg, MVT::i32); - Rsrc = buildScratchRSRC(CurDAG, DL, CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64)); + Rsrc = buildScratchRSRC(CurDAG, DL, + CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, + MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64)); SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32); diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index b66bcf52a54..ec259f11feb 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -743,16 +743,9 @@ static SDNode *findUser(SDValue Value, unsigned Opcode) { SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const { - MachineFunction &MF = DAG.getMachineFunction(); - const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( - getTargetMachine().getSubtargetImpl()->getInstrInfo()); - const SIRegisterInfo &TRI = TII->getRegisterInfo(); FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op); unsigned FrameIndex = FINode->getIndex(); - CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass, - TRI.getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET), MVT::i32); - return DAG.getTargetFrameIndex(FrameIndex, MVT::i32); } diff --git a/llvm/test/CodeGen/R600/store-vector-ptrs.ll b/llvm/test/CodeGen/R600/store-vector-ptrs.ll index 41c5edc280d..b2ea8468d79 100644 --- a/llvm/test/CodeGen/R600/store-vector-ptrs.ll +++ b/llvm/test/CodeGen/R600/store-vector-ptrs.ll @@ -1,9 +1,11 @@ -; REQUIRES: asserts -; XFAIL: * ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s +; This tests for a bug that caused a crash in +; AMDGPUDAGToDAGISel::SelectMUBUFScratch() which is used for selecting +; scratch loads and stores. +; CHECK-LABEL: @store_vector_ptrs define void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind { %p = getelementptr <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> store <4 x i32*> %p, <4 x i32*>* %out ret void -}
\ No newline at end of file +} |
