diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h | 10 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 |
2 files changed, 12 insertions, 4 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index fcd6e1a3452..5e38b6195c3 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -87,12 +87,20 @@ private: // Note: we would need to do something so that we can recognize such operand // as constants. // 3. Create the generic instruction. - bool translateADD(const Instruction &Inst); bool translateBr(const Instruction &Inst); bool translateReturn(const Instruction &Inst); + /// Translate \p Inst into a binary operation \p Opcode. + /// Insert the newly translated instruction right where the MIRBuilder + /// is set. + /// + /// \pre \p Inst is a binary operation. + /// + /// \return true if the translation succeeded. + bool translateBinaryOp(unsigned Opcode, const Instruction &Inst); + // Builder for machine instruction a la IRBuilder. // I.e., compared to regular MIBuilder, this one also inserts the instruction // in the current block, it can creates block, etc., basically a kind of diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 98af7608592..ea11b316255 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -61,7 +61,7 @@ MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) { return *MBB; } -bool IRTranslator::translateADD(const Instruction &Inst) { +bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) { // Get or create a virtual register for each value. // Unless the value is a Constant => loadimm cst? // or inline constant each time? @@ -69,7 +69,7 @@ bool IRTranslator::translateADD(const Instruction &Inst) { unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0)); unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1)); unsigned Res = getOrCreateVReg(Inst); - MIRBuilder.buildInstr(TargetOpcode::G_ADD, Inst.getType(), Res, Op0, Op1); + MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1); return true; } @@ -103,7 +103,7 @@ bool IRTranslator::translate(const Instruction &Inst) { MIRBuilder.setDebugLoc(Inst.getDebugLoc()); switch(Inst.getOpcode()) { case Instruction::Add: - return translateADD(Inst); + return translateBinaryOp(TargetOpcode::G_ADD, Inst); case Instruction::Br: return translateBr(Inst); case Instruction::Ret: |
