diff options
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vector-urem.ll | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/vector-urem.ll b/llvm/test/Transforms/InstCombine/vector-urem.ll index bf538d0ea80..eede6807d2e 100644 --- a/llvm/test/Transforms/InstCombine/vector-urem.ll +++ b/llvm/test/Transforms/InstCombine/vector-urem.ll @@ -19,3 +19,57 @@ define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) { ret <4 x i32> %1 } +define <4 x i32> @test_v4i32_const_pow2_undef(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_const_pow2_undef( +; CHECK-NEXT: ret <4 x i32> undef +; + %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef> + ret <4 x i32> %1 +} + +define <4 x i32> @test_v4i32_one(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_one( +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1> +; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[TMP2]] +; + %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %a0 + ret <4 x i32> %1 +} + +define <4 x i32> @test_v4i32_one_undef(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_one_undef( +; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, [[A0:%.*]] +; CHECK-NEXT: ret <4 x i32> [[TMP1]] +; + %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, %a0 + ret <4 x i32> %1 +} + +define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_negconstsplat( +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3> +; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[A0]], <i32 3, i32 3, i32 3, i32 3> +; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A0]], <4 x i32> [[TMP2]] +; CHECK-NEXT: ret <4 x i32> [[TMP3]] +; + %1 = urem <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3> + ret <4 x i32> %1 +} + +define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_negconst( +; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9> +; CHECK-NEXT: ret <4 x i32> [[TMP1]] +; + %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9> + ret <4 x i32> %1 +} + +define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) { +; CHECK-LABEL: @test_v4i32_negconst_undef( +; CHECK-NEXT: ret <4 x i32> undef +; + %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef> + ret <4 x i32> %1 +} |
