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-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.cpp92
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLowering.h1
-rw-r--r--llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp6
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPatterns.td22
-rw-r--r--llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll2
-rw-r--r--llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll376
-rw-r--r--llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll232
7 files changed, 663 insertions, 68 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 9535d0f259e..b0781c1811d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2109,8 +2109,13 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ANY_EXTEND, T, Custom);
setOperationAction(ISD::SIGN_EXTEND, T, Custom);
setOperationAction(ISD::ZERO_EXTEND, T, Custom);
- if (T != ByteV)
+ if (T != ByteV) {
setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, T, Custom);
+ // HVX only has shifts of words and halfwords.
+ setOperationAction(ISD::SRA, T, Custom);
+ setOperationAction(ISD::SHL, T, Custom);
+ setOperationAction(ISD::SRL, T, Custom);
+ }
}
for (MVT T : LegalV) {
@@ -2523,76 +2528,37 @@ HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
return SDValue();
}
-// If BUILD_VECTOR has same base element repeated several times,
-// report true.
-static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
- unsigned NElts = BVN->getNumOperands();
- SDValue V0 = BVN->getOperand(0);
-
- for (unsigned i = 1, e = NElts; i != e; ++i) {
- if (BVN->getOperand(i) != V0)
- return false;
- }
- return true;
-}
-
// Lower a vector shift. Try to convert
// <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
// <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
SDValue
HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
- BuildVectorSDNode *BVN = nullptr;
- SDValue V1 = Op.getOperand(0);
- SDValue V2 = Op.getOperand(1);
- SDValue V3;
- SDLoc dl(Op);
- EVT VT = Op.getValueType();
-
- if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
- isCommonSplatElement(BVN))
- V3 = V2;
- else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
- isCommonSplatElement(BVN))
- V3 = V1;
- else
- return SDValue();
-
- SDValue CommonSplat = BVN->getOperand(0);
- SDValue Result;
-
- if (VT.getSimpleVT() == MVT::v4i16) {
- switch (Op.getOpcode()) {
- case ISD::SRA:
- Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
- break;
- case ISD::SHL:
- Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
- break;
- case ISD::SRL:
- Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
- break;
- default:
- return SDValue();
- }
- } else if (VT.getSimpleVT() == MVT::v2i32) {
- switch (Op.getOpcode()) {
- case ISD::SRA:
- Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
- break;
- case ISD::SHL:
- Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
- break;
- case ISD::SRL:
- Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
- break;
- default:
- return SDValue();
+ const SDLoc dl(Op);
+
+ if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
+ if (SDValue S = BVN->getSplatValue()) {
+ unsigned NewOpc;
+ switch (Op.getOpcode()) {
+ case ISD::SHL:
+ NewOpc = HexagonISD::VASL;
+ break;
+ case ISD::SRA:
+ NewOpc = HexagonISD::VASR;
+ break;
+ case ISD::SRL:
+ NewOpc = HexagonISD::VLSR;
+ break;
+ default:
+ llvm_unreachable("Unexpected shift opcode");
+ }
+ return DAG.getNode(NewOpc, dl, ty(Op), Op.getOperand(0), S);
}
- } else {
- return SDValue();
}
- return DAG.getNode(ISD::BITCAST, dl, VT, Result);
+ if (Subtarget.useHVXOps() && Subtarget.isHVXVectorType(ty(Op)))
+ return LowerHvxShift(Op, DAG);
+
+ return SDValue();
}
SDValue
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
index 0bc230728d8..6a1105dc158 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h
@@ -402,6 +402,7 @@ namespace HexagonISD {
SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 1be3ce8366c..b17747372f0 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -1103,3 +1103,9 @@ HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG);
return DAG.getZeroExtendVectorInReg(Op.getOperand(0), SDLoc(Op), ty(Op));
}
+
+SDValue
+HexagonTargetLowering::LowerHvxShift(SDValue Op, SelectionDAG &DAG) const {
+ return Op;
+}
+
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index bcedf879dea..06e23e24991 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3095,19 +3095,33 @@ let Predicates = [UseHVX] in {
def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
(V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i8)),
- (V6_vasrh (V6_vaslh HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
+ (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v16i16)),
- (V6_vasrh (V6_vaslh HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
+ (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
}
let Predicates = [UseHVX,UseHVX128B] in {
def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v64i8)),
(V6_vasrh (V6_vaslh HVI16:$Vs, (A2_tfrsi 8)), (A2_tfrsi 8))>;
def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
- (V6_vasrh (V6_vaslh HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
+ (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 24)), (A2_tfrsi 24))>;
def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i16)),
- (V6_vasrh (V6_vaslh HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
+ (V6_vasrw (V6_vaslw HVI32:$Vs, (A2_tfrsi 16)), (A2_tfrsi 16))>;
}
+ def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
+ def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
+ def: Pat<(HexagonVASR HVI16:$Vs, I32:$Rt), (V6_vasrh HvxVR:$Vs, I32:$Rt)>;
+ def: Pat<(HexagonVASR HVI32:$Vs, I32:$Rt), (V6_vasrw HvxVR:$Vs, I32:$Rt)>;
+ def: Pat<(HexagonVLSR HVI16:$Vs, I32:$Rt), (V6_vlsrh HvxVR:$Vs, I32:$Rt)>;
+ def: Pat<(HexagonVLSR HVI32:$Vs, I32:$Rt), (V6_vlsrw HvxVR:$Vs, I32:$Rt)>;
+
+ def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(sra HVI32:$Vs, HVI32:$Vt), (V6_vasrwv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
+ def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
+
def: Pat<(VecI8 (trunc HWI16:$Vss)),
(V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
def: Pat<(VecI16 (trunc HWI32:$Vss)),
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
index f1988116de3..91d95c0e7d5 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-build-undef.ll
@@ -5,7 +5,7 @@
; splat, but had no source value.
;
; Check that this compiles successfully.
-; CHECK: vxor
+; CHECK: vsplat
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
new file mode 100644
index 00000000000..2bf1ba903a4
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
@@ -0,0 +1,376 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: test0000:
+; CHECK: v0.h = vasl(v0.h,r0)
+define <64 x i16> @test0000(<64 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <64 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <64 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <64 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <64 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <64 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <64 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <64 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <64 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <64 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <64 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <64 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <64 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <64 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <64 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <64 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <64 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <64 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <64 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <64 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <64 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <64 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <64 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <64 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <64 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <64 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <64 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <64 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <64 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <64 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <64 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <64 x i16> %b30, i16 %a1, i32 31
+ %b32 = insertelement <64 x i16> %b31, i16 %a1, i32 32
+ %b33 = insertelement <64 x i16> %b32, i16 %a1, i32 33
+ %b34 = insertelement <64 x i16> %b33, i16 %a1, i32 34
+ %b35 = insertelement <64 x i16> %b34, i16 %a1, i32 35
+ %b36 = insertelement <64 x i16> %b35, i16 %a1, i32 36
+ %b37 = insertelement <64 x i16> %b36, i16 %a1, i32 37
+ %b38 = insertelement <64 x i16> %b37, i16 %a1, i32 38
+ %b39 = insertelement <64 x i16> %b38, i16 %a1, i32 39
+ %b40 = insertelement <64 x i16> %b39, i16 %a1, i32 40
+ %b41 = insertelement <64 x i16> %b40, i16 %a1, i32 41
+ %b42 = insertelement <64 x i16> %b41, i16 %a1, i32 42
+ %b43 = insertelement <64 x i16> %b42, i16 %a1, i32 43
+ %b44 = insertelement <64 x i16> %b43, i16 %a1, i32 44
+ %b45 = insertelement <64 x i16> %b44, i16 %a1, i32 45
+ %b46 = insertelement <64 x i16> %b45, i16 %a1, i32 46
+ %b47 = insertelement <64 x i16> %b46, i16 %a1, i32 47
+ %b48 = insertelement <64 x i16> %b47, i16 %a1, i32 48
+ %b49 = insertelement <64 x i16> %b48, i16 %a1, i32 49
+ %b50 = insertelement <64 x i16> %b49, i16 %a1, i32 50
+ %b51 = insertelement <64 x i16> %b50, i16 %a1, i32 51
+ %b52 = insertelement <64 x i16> %b51, i16 %a1, i32 52
+ %b53 = insertelement <64 x i16> %b52, i16 %a1, i32 53
+ %b54 = insertelement <64 x i16> %b53, i16 %a1, i32 54
+ %b55 = insertelement <64 x i16> %b54, i16 %a1, i32 55
+ %b56 = insertelement <64 x i16> %b55, i16 %a1, i32 56
+ %b57 = insertelement <64 x i16> %b56, i16 %a1, i32 57
+ %b58 = insertelement <64 x i16> %b57, i16 %a1, i32 58
+ %b59 = insertelement <64 x i16> %b58, i16 %a1, i32 59
+ %b60 = insertelement <64 x i16> %b59, i16 %a1, i32 60
+ %b61 = insertelement <64 x i16> %b60, i16 %a1, i32 61
+ %b62 = insertelement <64 x i16> %b61, i16 %a1, i32 62
+ %b63 = insertelement <64 x i16> %b62, i16 %a1, i32 63
+ %v0 = shl <64 x i16> %a0, %b63
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0001:
+; CHECK: v0.h = vasr(v0.h,r0)
+define <64 x i16> @test0001(<64 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <64 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <64 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <64 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <64 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <64 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <64 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <64 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <64 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <64 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <64 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <64 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <64 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <64 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <64 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <64 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <64 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <64 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <64 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <64 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <64 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <64 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <64 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <64 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <64 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <64 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <64 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <64 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <64 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <64 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <64 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <64 x i16> %b30, i16 %a1, i32 31
+ %b32 = insertelement <64 x i16> %b31, i16 %a1, i32 32
+ %b33 = insertelement <64 x i16> %b32, i16 %a1, i32 33
+ %b34 = insertelement <64 x i16> %b33, i16 %a1, i32 34
+ %b35 = insertelement <64 x i16> %b34, i16 %a1, i32 35
+ %b36 = insertelement <64 x i16> %b35, i16 %a1, i32 36
+ %b37 = insertelement <64 x i16> %b36, i16 %a1, i32 37
+ %b38 = insertelement <64 x i16> %b37, i16 %a1, i32 38
+ %b39 = insertelement <64 x i16> %b38, i16 %a1, i32 39
+ %b40 = insertelement <64 x i16> %b39, i16 %a1, i32 40
+ %b41 = insertelement <64 x i16> %b40, i16 %a1, i32 41
+ %b42 = insertelement <64 x i16> %b41, i16 %a1, i32 42
+ %b43 = insertelement <64 x i16> %b42, i16 %a1, i32 43
+ %b44 = insertelement <64 x i16> %b43, i16 %a1, i32 44
+ %b45 = insertelement <64 x i16> %b44, i16 %a1, i32 45
+ %b46 = insertelement <64 x i16> %b45, i16 %a1, i32 46
+ %b47 = insertelement <64 x i16> %b46, i16 %a1, i32 47
+ %b48 = insertelement <64 x i16> %b47, i16 %a1, i32 48
+ %b49 = insertelement <64 x i16> %b48, i16 %a1, i32 49
+ %b50 = insertelement <64 x i16> %b49, i16 %a1, i32 50
+ %b51 = insertelement <64 x i16> %b50, i16 %a1, i32 51
+ %b52 = insertelement <64 x i16> %b51, i16 %a1, i32 52
+ %b53 = insertelement <64 x i16> %b52, i16 %a1, i32 53
+ %b54 = insertelement <64 x i16> %b53, i16 %a1, i32 54
+ %b55 = insertelement <64 x i16> %b54, i16 %a1, i32 55
+ %b56 = insertelement <64 x i16> %b55, i16 %a1, i32 56
+ %b57 = insertelement <64 x i16> %b56, i16 %a1, i32 57
+ %b58 = insertelement <64 x i16> %b57, i16 %a1, i32 58
+ %b59 = insertelement <64 x i16> %b58, i16 %a1, i32 59
+ %b60 = insertelement <64 x i16> %b59, i16 %a1, i32 60
+ %b61 = insertelement <64 x i16> %b60, i16 %a1, i32 61
+ %b62 = insertelement <64 x i16> %b61, i16 %a1, i32 62
+ %b63 = insertelement <64 x i16> %b62, i16 %a1, i32 63
+ %v0 = ashr <64 x i16> %a0, %b63
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0002:
+; CHECK: v0.uh = vlsr(v0.uh,r0)
+define <64 x i16> @test0002(<64 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <64 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <64 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <64 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <64 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <64 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <64 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <64 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <64 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <64 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <64 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <64 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <64 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <64 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <64 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <64 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <64 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <64 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <64 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <64 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <64 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <64 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <64 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <64 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <64 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <64 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <64 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <64 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <64 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <64 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <64 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <64 x i16> %b30, i16 %a1, i32 31
+ %b32 = insertelement <64 x i16> %b31, i16 %a1, i32 32
+ %b33 = insertelement <64 x i16> %b32, i16 %a1, i32 33
+ %b34 = insertelement <64 x i16> %b33, i16 %a1, i32 34
+ %b35 = insertelement <64 x i16> %b34, i16 %a1, i32 35
+ %b36 = insertelement <64 x i16> %b35, i16 %a1, i32 36
+ %b37 = insertelement <64 x i16> %b36, i16 %a1, i32 37
+ %b38 = insertelement <64 x i16> %b37, i16 %a1, i32 38
+ %b39 = insertelement <64 x i16> %b38, i16 %a1, i32 39
+ %b40 = insertelement <64 x i16> %b39, i16 %a1, i32 40
+ %b41 = insertelement <64 x i16> %b40, i16 %a1, i32 41
+ %b42 = insertelement <64 x i16> %b41, i16 %a1, i32 42
+ %b43 = insertelement <64 x i16> %b42, i16 %a1, i32 43
+ %b44 = insertelement <64 x i16> %b43, i16 %a1, i32 44
+ %b45 = insertelement <64 x i16> %b44, i16 %a1, i32 45
+ %b46 = insertelement <64 x i16> %b45, i16 %a1, i32 46
+ %b47 = insertelement <64 x i16> %b46, i16 %a1, i32 47
+ %b48 = insertelement <64 x i16> %b47, i16 %a1, i32 48
+ %b49 = insertelement <64 x i16> %b48, i16 %a1, i32 49
+ %b50 = insertelement <64 x i16> %b49, i16 %a1, i32 50
+ %b51 = insertelement <64 x i16> %b50, i16 %a1, i32 51
+ %b52 = insertelement <64 x i16> %b51, i16 %a1, i32 52
+ %b53 = insertelement <64 x i16> %b52, i16 %a1, i32 53
+ %b54 = insertelement <64 x i16> %b53, i16 %a1, i32 54
+ %b55 = insertelement <64 x i16> %b54, i16 %a1, i32 55
+ %b56 = insertelement <64 x i16> %b55, i16 %a1, i32 56
+ %b57 = insertelement <64 x i16> %b56, i16 %a1, i32 57
+ %b58 = insertelement <64 x i16> %b57, i16 %a1, i32 58
+ %b59 = insertelement <64 x i16> %b58, i16 %a1, i32 59
+ %b60 = insertelement <64 x i16> %b59, i16 %a1, i32 60
+ %b61 = insertelement <64 x i16> %b60, i16 %a1, i32 61
+ %b62 = insertelement <64 x i16> %b61, i16 %a1, i32 62
+ %b63 = insertelement <64 x i16> %b62, i16 %a1, i32 63
+ %v0 = lshr <64 x i16> %a0, %b63
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0010:
+; CHECK: v0.w = vasl(v0.w,r0)
+define <32 x i32> @test0010(<32 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <32 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <32 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <32 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <32 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <32 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <32 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <32 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <32 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <32 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <32 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <32 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <32 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <32 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <32 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <32 x i32> %b14, i32 %a1, i32 15
+ %b16 = insertelement <32 x i32> %b15, i32 %a1, i32 16
+ %b17 = insertelement <32 x i32> %b16, i32 %a1, i32 17
+ %b18 = insertelement <32 x i32> %b17, i32 %a1, i32 18
+ %b19 = insertelement <32 x i32> %b18, i32 %a1, i32 19
+ %b20 = insertelement <32 x i32> %b19, i32 %a1, i32 20
+ %b21 = insertelement <32 x i32> %b20, i32 %a1, i32 21
+ %b22 = insertelement <32 x i32> %b21, i32 %a1, i32 22
+ %b23 = insertelement <32 x i32> %b22, i32 %a1, i32 23
+ %b24 = insertelement <32 x i32> %b23, i32 %a1, i32 24
+ %b25 = insertelement <32 x i32> %b24, i32 %a1, i32 25
+ %b26 = insertelement <32 x i32> %b25, i32 %a1, i32 26
+ %b27 = insertelement <32 x i32> %b26, i32 %a1, i32 27
+ %b28 = insertelement <32 x i32> %b27, i32 %a1, i32 28
+ %b29 = insertelement <32 x i32> %b28, i32 %a1, i32 29
+ %b30 = insertelement <32 x i32> %b29, i32 %a1, i32 30
+ %b31 = insertelement <32 x i32> %b30, i32 %a1, i32 31
+ %v0 = shl <32 x i32> %a0, %b31
+ ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: test0011:
+; CHECK: v0.w = vasr(v0.w,r0)
+define <32 x i32> @test0011(<32 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <32 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <32 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <32 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <32 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <32 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <32 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <32 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <32 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <32 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <32 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <32 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <32 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <32 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <32 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <32 x i32> %b14, i32 %a1, i32 15
+ %b16 = insertelement <32 x i32> %b15, i32 %a1, i32 16
+ %b17 = insertelement <32 x i32> %b16, i32 %a1, i32 17
+ %b18 = insertelement <32 x i32> %b17, i32 %a1, i32 18
+ %b19 = insertelement <32 x i32> %b18, i32 %a1, i32 19
+ %b20 = insertelement <32 x i32> %b19, i32 %a1, i32 20
+ %b21 = insertelement <32 x i32> %b20, i32 %a1, i32 21
+ %b22 = insertelement <32 x i32> %b21, i32 %a1, i32 22
+ %b23 = insertelement <32 x i32> %b22, i32 %a1, i32 23
+ %b24 = insertelement <32 x i32> %b23, i32 %a1, i32 24
+ %b25 = insertelement <32 x i32> %b24, i32 %a1, i32 25
+ %b26 = insertelement <32 x i32> %b25, i32 %a1, i32 26
+ %b27 = insertelement <32 x i32> %b26, i32 %a1, i32 27
+ %b28 = insertelement <32 x i32> %b27, i32 %a1, i32 28
+ %b29 = insertelement <32 x i32> %b28, i32 %a1, i32 29
+ %b30 = insertelement <32 x i32> %b29, i32 %a1, i32 30
+ %b31 = insertelement <32 x i32> %b30, i32 %a1, i32 31
+ %v0 = ashr <32 x i32> %a0, %b31
+ ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: test0012:
+; CHECK: v0.uw = vlsr(v0.uw,r0)
+define <32 x i32> @test0012(<32 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <32 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <32 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <32 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <32 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <32 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <32 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <32 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <32 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <32 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <32 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <32 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <32 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <32 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <32 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <32 x i32> %b14, i32 %a1, i32 15
+ %b16 = insertelement <32 x i32> %b15, i32 %a1, i32 16
+ %b17 = insertelement <32 x i32> %b16, i32 %a1, i32 17
+ %b18 = insertelement <32 x i32> %b17, i32 %a1, i32 18
+ %b19 = insertelement <32 x i32> %b18, i32 %a1, i32 19
+ %b20 = insertelement <32 x i32> %b19, i32 %a1, i32 20
+ %b21 = insertelement <32 x i32> %b20, i32 %a1, i32 21
+ %b22 = insertelement <32 x i32> %b21, i32 %a1, i32 22
+ %b23 = insertelement <32 x i32> %b22, i32 %a1, i32 23
+ %b24 = insertelement <32 x i32> %b23, i32 %a1, i32 24
+ %b25 = insertelement <32 x i32> %b24, i32 %a1, i32 25
+ %b26 = insertelement <32 x i32> %b25, i32 %a1, i32 26
+ %b27 = insertelement <32 x i32> %b26, i32 %a1, i32 27
+ %b28 = insertelement <32 x i32> %b27, i32 %a1, i32 28
+ %b29 = insertelement <32 x i32> %b28, i32 %a1, i32 29
+ %b30 = insertelement <32 x i32> %b29, i32 %a1, i32 30
+ %b31 = insertelement <32 x i32> %b30, i32 %a1, i32 31
+ %v0 = lshr <32 x i32> %a0, %b31
+ ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: test0020:
+; CHECK: v0.h = vasl(v0.h,v1.h)
+define <64 x i16> @test0020(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %v0 = shl <64 x i16> %a0, %a1
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0021:
+; CHECK: v0.h = vasr(v0.h,v1.h)
+define <64 x i16> @test0021(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %v0 = ashr <64 x i16> %a0, %a1
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0022:
+; CHECK: v0.h = vlsr(v0.h,v1.h)
+define <64 x i16> @test0022(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %v0 = lshr <64 x i16> %a0, %a1
+ ret <64 x i16> %v0
+}
+
+; CHECK-LABEL: test0030:
+; CHECK: v0.w = vasl(v0.w,v1.w)
+define <32 x i32> @test0030(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %v0 = shl <32 x i32> %a0, %a1
+ ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: test0031:
+; CHECK: v0.w = vasr(v0.w,v1.w)
+define <32 x i32> @test0031(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %v0 = ashr <32 x i32> %a0, %a1
+ ret <32 x i32> %v0
+}
+
+; CHECK-LABEL: test0032:
+; CHECK: v0.w = vlsr(v0.w,v1.w)
+define <32 x i32> @test0032(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %v0 = lshr <32 x i32> %a0, %a1
+ ret <32 x i32> %v0
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
+
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
new file mode 100644
index 00000000000..a43a854aac7
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
@@ -0,0 +1,232 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: test0000:
+; CHECK: v0.h = vasl(v0.h,r0)
+define <32 x i16> @test0000(<32 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <32 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <32 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <32 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <32 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <32 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <32 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <32 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <32 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <32 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <32 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <32 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <32 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <32 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <32 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <32 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <32 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <32 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <32 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <32 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <32 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <32 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <32 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <32 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <32 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <32 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <32 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <32 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <32 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <32 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <32 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <32 x i16> %b30, i16 %a1, i32 31
+ %v0 = shl <32 x i16> %a0, %b31
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0001:
+; CHECK: v0.h = vasr(v0.h,r0)
+define <32 x i16> @test0001(<32 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <32 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <32 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <32 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <32 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <32 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <32 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <32 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <32 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <32 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <32 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <32 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <32 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <32 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <32 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <32 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <32 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <32 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <32 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <32 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <32 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <32 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <32 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <32 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <32 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <32 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <32 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <32 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <32 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <32 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <32 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <32 x i16> %b30, i16 %a1, i32 31
+ %v0 = ashr <32 x i16> %a0, %b31
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0002:
+; CHECK: v0.uh = vlsr(v0.uh,r0)
+define <32 x i16> @test0002(<32 x i16> %a0, i16 %a1) #0 {
+ %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
+ %b1 = insertelement <32 x i16> %b0, i16 %a1, i32 1
+ %b2 = insertelement <32 x i16> %b1, i16 %a1, i32 2
+ %b3 = insertelement <32 x i16> %b2, i16 %a1, i32 3
+ %b4 = insertelement <32 x i16> %b3, i16 %a1, i32 4
+ %b5 = insertelement <32 x i16> %b4, i16 %a1, i32 5
+ %b6 = insertelement <32 x i16> %b5, i16 %a1, i32 6
+ %b7 = insertelement <32 x i16> %b6, i16 %a1, i32 7
+ %b8 = insertelement <32 x i16> %b7, i16 %a1, i32 8
+ %b9 = insertelement <32 x i16> %b8, i16 %a1, i32 9
+ %b10 = insertelement <32 x i16> %b9, i16 %a1, i32 10
+ %b11 = insertelement <32 x i16> %b10, i16 %a1, i32 11
+ %b12 = insertelement <32 x i16> %b11, i16 %a1, i32 12
+ %b13 = insertelement <32 x i16> %b12, i16 %a1, i32 13
+ %b14 = insertelement <32 x i16> %b13, i16 %a1, i32 14
+ %b15 = insertelement <32 x i16> %b14, i16 %a1, i32 15
+ %b16 = insertelement <32 x i16> %b15, i16 %a1, i32 16
+ %b17 = insertelement <32 x i16> %b16, i16 %a1, i32 17
+ %b18 = insertelement <32 x i16> %b17, i16 %a1, i32 18
+ %b19 = insertelement <32 x i16> %b18, i16 %a1, i32 19
+ %b20 = insertelement <32 x i16> %b19, i16 %a1, i32 20
+ %b21 = insertelement <32 x i16> %b20, i16 %a1, i32 21
+ %b22 = insertelement <32 x i16> %b21, i16 %a1, i32 22
+ %b23 = insertelement <32 x i16> %b22, i16 %a1, i32 23
+ %b24 = insertelement <32 x i16> %b23, i16 %a1, i32 24
+ %b25 = insertelement <32 x i16> %b24, i16 %a1, i32 25
+ %b26 = insertelement <32 x i16> %b25, i16 %a1, i32 26
+ %b27 = insertelement <32 x i16> %b26, i16 %a1, i32 27
+ %b28 = insertelement <32 x i16> %b27, i16 %a1, i32 28
+ %b29 = insertelement <32 x i16> %b28, i16 %a1, i32 29
+ %b30 = insertelement <32 x i16> %b29, i16 %a1, i32 30
+ %b31 = insertelement <32 x i16> %b30, i16 %a1, i32 31
+ %v0 = lshr <32 x i16> %a0, %b31
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0010:
+; CHECK: v0.w = vasl(v0.w,r0)
+define <16 x i32> @test0010(<16 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <16 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <16 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <16 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <16 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <16 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <16 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <16 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <16 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <16 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <16 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <16 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <16 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <16 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <16 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <16 x i32> %b14, i32 %a1, i32 15
+ %v0 = shl <16 x i32> %a0, %b15
+ ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test0011:
+; CHECK: v0.w = vasr(v0.w,r0)
+define <16 x i32> @test0011(<16 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <16 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <16 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <16 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <16 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <16 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <16 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <16 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <16 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <16 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <16 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <16 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <16 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <16 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <16 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <16 x i32> %b14, i32 %a1, i32 15
+ %v0 = ashr <16 x i32> %a0, %b15
+ ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test0012:
+; CHECK: v0.uw = vlsr(v0.uw,r0)
+define <16 x i32> @test0012(<16 x i32> %a0, i32 %a1) #0 {
+ %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
+ %b1 = insertelement <16 x i32> %b0, i32 %a1, i32 1
+ %b2 = insertelement <16 x i32> %b1, i32 %a1, i32 2
+ %b3 = insertelement <16 x i32> %b2, i32 %a1, i32 3
+ %b4 = insertelement <16 x i32> %b3, i32 %a1, i32 4
+ %b5 = insertelement <16 x i32> %b4, i32 %a1, i32 5
+ %b6 = insertelement <16 x i32> %b5, i32 %a1, i32 6
+ %b7 = insertelement <16 x i32> %b6, i32 %a1, i32 7
+ %b8 = insertelement <16 x i32> %b7, i32 %a1, i32 8
+ %b9 = insertelement <16 x i32> %b8, i32 %a1, i32 9
+ %b10 = insertelement <16 x i32> %b9, i32 %a1, i32 10
+ %b11 = insertelement <16 x i32> %b10, i32 %a1, i32 11
+ %b12 = insertelement <16 x i32> %b11, i32 %a1, i32 12
+ %b13 = insertelement <16 x i32> %b12, i32 %a1, i32 13
+ %b14 = insertelement <16 x i32> %b13, i32 %a1, i32 14
+ %b15 = insertelement <16 x i32> %b14, i32 %a1, i32 15
+ %v0 = lshr <16 x i32> %a0, %b15
+ ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test0020:
+; CHECK: v0.h = vasl(v0.h,v1.h)
+define <32 x i16> @test0020(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %v0 = shl <32 x i16> %a0, %a1
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0021:
+; CHECK: v0.h = vasr(v0.h,v1.h)
+define <32 x i16> @test0021(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %v0 = ashr <32 x i16> %a0, %a1
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0022:
+; CHECK: v0.h = vlsr(v0.h,v1.h)
+define <32 x i16> @test0022(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %v0 = lshr <32 x i16> %a0, %a1
+ ret <32 x i16> %v0
+}
+
+; CHECK-LABEL: test0030:
+; CHECK: v0.w = vasl(v0.w,v1.w)
+define <16 x i32> @test0030(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %v0 = shl <16 x i32> %a0, %a1
+ ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test0031:
+; CHECK: v0.w = vasr(v0.w,v1.w)
+define <16 x i32> @test0031(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %v0 = ashr <16 x i32> %a0, %a1
+ ret <16 x i32> %v0
+}
+
+; CHECK-LABEL: test0032:
+; CHECK: v0.w = vlsr(v0.w,v1.w)
+define <16 x i32> @test0032(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %v0 = lshr <16 x i32> %a0, %a1
+ ret <16 x i32> %v0
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
+
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