diff options
| -rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 35 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vector-casts-0.ll (renamed from llvm/test/Transforms/InstCombine/vector-casts.ll) | 0 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/vector-casts-1.ll | 15 | 
3 files changed, 32 insertions, 18 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index d77c2b5fc48..8dc8659648f 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -5967,9 +5967,9 @@ Instruction *InstCombiner::visitICmpInst(ICmpInst &I) {    unsigned BitWidth = 0;    if (TD) -    BitWidth = TD->getTypeSizeInBits(Ty); -  else if (isa<IntegerType>(Ty)) -    BitWidth = Ty->getPrimitiveSizeInBits(); +    BitWidth = TD->getTypeSizeInBits(Ty->getScalarType()); +  else if (Ty->isIntOrIntVector()) +    BitWidth = Ty->getScalarSizeInBits();    bool isSignBit = false; @@ -7234,18 +7234,16 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) {    if (ConstantInt *CSI = dyn_cast<ConstantInt>(Op0))      if (CSI->isAllOnesValue())        return ReplaceInstUsesWith(I, CSI); -   +    // See if we can turn a signed shr into an unsigned shr. -  if (!isa<VectorType>(I.getType())) { -    if (MaskedValueIsZero(Op0, -                      APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()))) -      return BinaryOperator::CreateLShr(Op0, I.getOperand(1)); - -    // Arithmetic shifting an all-sign-bit value is a no-op. -    unsigned NumSignBits = ComputeNumSignBits(Op0); -    if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits()) -      return ReplaceInstUsesWith(I, Op0); -  } +  if (MaskedValueIsZero(Op0, +                        APInt::getSignBit(I.getType()->getScalarSizeInBits()))) +    return BinaryOperator::CreateLShr(Op0, I.getOperand(1)); + +  // Arithmetic shifting an all-sign-bit value is a no-op. +  unsigned NumSignBits = ComputeNumSignBits(Op0); +  if (NumSignBits == Op0->getType()->getScalarSizeInBits()) +    return ReplaceInstUsesWith(I, Op0);    return 0;  } @@ -7295,7 +7293,7 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,    // See if we can simplify any instructions used by the instruction whose sole     // purpose is to compute bits we don't care about. -  uint32_t TypeBits = Op0->getType()->getPrimitiveSizeInBits(); +  uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();    // shl i32 X, 32 = 0 and srl i8 Y, 9 = 0, ... just don't eliminate    // a signed shift. @@ -7344,8 +7342,8 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,        // part of the register be zeros.  Emulate this by inserting an AND to        // clear the top bits as needed.  This 'and' will usually be zapped by        // other xforms later if dead. -      unsigned SrcSize = TrOp->getType()->getPrimitiveSizeInBits(); -      unsigned DstSize = TI->getType()->getPrimitiveSizeInBits(); +      unsigned SrcSize = TrOp->getType()->getScalarSizeInBits(); +      unsigned DstSize = TI->getType()->getScalarSizeInBits();        APInt MaskV(APInt::getLowBitsSet(SrcSize, DstSize));        // The mask we constructed says what the trunc would do if occurring @@ -8380,7 +8378,8 @@ Instruction *InstCombiner::visitTrunc(TruncInst &CI) {    uint32_t SrcBitWidth = Src->getType()->getScalarSizeInBits();    // Canonicalize trunc x to i1 -> (icmp ne (and x, 1), 0) -  if (!isa<VectorType>(Ty) && DestBitWidth == 1) { +  if (DestBitWidth == 1 && +      isa<VectorType>(Ty) == isa<VectorType>(Src->getType())) {      Constant *One = ConstantInt::get(Src->getType(), 1);      Src = InsertNewInstBefore(BinaryOperator::CreateAnd(Src, One, "tmp"), CI);      Value *Zero = Constant::getNullValue(Src->getType()); diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts-0.ll index ae5b8a9c7c4..ae5b8a9c7c4 100644 --- a/llvm/test/Transforms/InstCombine/vector-casts.ll +++ b/llvm/test/Transforms/InstCombine/vector-casts-0.ll diff --git a/llvm/test/Transforms/InstCombine/vector-casts-1.ll b/llvm/test/Transforms/InstCombine/vector-casts-1.ll new file mode 100644 index 00000000000..a73a84ac1e0 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/vector-casts-1.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | opt -instcombine > %t +; RUN: not grep trunc %t +; RUN: not grep ashr %t + +; This turns into a&1 != 0 +define <2 x i1> @a(<2 x i64> %a) { +  %t = trunc <2 x i64> %a to <2 x i1> +  ret <2 x i1> %t +} +; The ashr turns into an lshr. +define <2 x i64> @b(<2 x i64> %a) { +  %b = and <2 x i64> %a, <i64 65535, i64 65535> +  %t = ashr <2 x i64> %b, <i64 1, i64 1> +  ret <2 x i64> %t +}  | 

