diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86FixupLEAs.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86PadShortFunction.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86TargetMachine.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86VZeroUpper.cpp | 3 |
5 files changed, 17 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index 1e7712c2df8..6c5b86f6196 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -150,6 +150,10 @@ FunctionPass *llvm::createX86FixupLEAs() { bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) { TM = &Func.getTarget(); + const X86Subtarget &ST = TM->getSubtarget<X86Subtarget>(); + if (!ST.LEAusesAG() && !ST.slowLEA()) + return false; + TII = static_cast<const X86InstrInfo*>(TM->getInstrInfo()); DEBUG(dbgs() << "Start X86FixupLEAs\n";); diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 8edce9fd462..6993577d19c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -5395,8 +5395,10 @@ namespace { const X86TargetMachine *TM = static_cast<const X86TargetMachine *>(&MF.getTarget()); - assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && - "X86-64 PIC uses RIP relative addressing"); + // Don't do anything if this is 64-bit as 64-bit PIC + // uses RIP relative addressing. + if (TM->getSubtarget<X86Subtarget>().is64Bit()) + return false; // Only emit a global base reg in PIC mode. if (TM->getRelocationModel() != Reloc::PIC_) diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp index 84521ccee48..6639875d07e 100644 --- a/llvm/lib/Target/X86/X86PadShortFunction.cpp +++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp @@ -17,6 +17,7 @@ #include "X86.h" #include "X86InstrInfo.h" +#include "X86Subtarget.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -101,6 +102,9 @@ bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) { } TM = &MF.getTarget(); + if (!TM->getSubtarget<X86Subtarget>().padShortFunctions()) + return false; + TII = TM->getInstrInfo(); // Search through basic blocks and mark the ones that have early returns diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 1970ffa0bd1..93760efe666 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -178,9 +178,7 @@ bool X86PassConfig::addInstSelector() { if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) addPass(createCleanupLocalDynamicTLSPass()); - // For 32-bit, prepend instructions to set the "global base reg" for PIC. - if (!getX86Subtarget().is64Bit()) - addPass(createX86GlobalBaseRegPass()); + addPass(createX86GlobalBaseRegPass()); return false; } @@ -206,19 +204,13 @@ bool X86PassConfig::addPreEmitPass() { ShouldPrint = true; } - if (getX86Subtarget().hasAVX() && UseVZeroUpper) { + if (UseVZeroUpper) { addPass(createX86IssueVZeroUpperPass()); ShouldPrint = true; } - if (getOptLevel() != CodeGenOpt::None && - getX86Subtarget().padShortFunctions()) { + if (getOptLevel() != CodeGenOpt::None) { addPass(createX86PadShortFunctions()); - ShouldPrint = true; - } - if (getOptLevel() != CodeGenOpt::None && - (getX86Subtarget().LEAusesAG() || - getX86Subtarget().slowLEA())){ addPass(createX86FixupLEAs()); ShouldPrint = true; } diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 945ea3e8817..0bb5f990cae 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -247,7 +247,8 @@ void VZeroUpperInserter::processBasicBlock(MachineBasicBlock &MBB) { /// runOnMachineFunction - Loop over all of the basic blocks, inserting /// vzero upper instructions before function calls. bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { - if (MF.getTarget().getSubtarget<X86Subtarget>().hasAVX512()) + const X86Subtarget &ST = MF.getTarget().getSubtarget<X86Subtarget>(); + if (!ST.hasAVX() || ST.hasAVX512()) return false; TII = MF.getTarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); |
