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-rw-r--r--lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp130
-rw-r--r--lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp6
-rw-r--r--lldb/source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp6
-rw-r--r--lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h1501
4 files changed, 1573 insertions, 70 deletions
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
index d839843a26e..64983a2404e 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
@@ -25,6 +25,8 @@
#include "lldb/Core/RegisterValue.h"
#include "lldb/Core/Scalar.h"
#include "lldb/Host/Endian.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Target/Thread.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Compiler.h"
@@ -101,7 +103,7 @@ static uint32_t g_fpu_regnums[] = {
static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception};
static size_t k_num_register_infos =
- llvm::array_lengthof(g_register_infos_arm64);
+ llvm::array_lengthof(g_register_infos_arm64_le);
RegisterContextDarwin_arm64::RegisterContextDarwin_arm64(
Thread &thread, uint32_t concrete_frame_idx)
@@ -129,7 +131,7 @@ const RegisterInfo *
RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) {
assert(k_num_register_infos == k_num_registers);
if (reg < k_num_registers)
- return &g_register_infos_arm64[reg];
+ return &g_register_infos_arm64_le[reg];
return NULL;
}
@@ -138,7 +140,7 @@ size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() {
}
const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() {
- return g_register_infos_arm64;
+ return g_register_infos_arm64_le;
}
// Number of registers in each register set
@@ -352,6 +354,46 @@ bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
value.SetUInt64(gpr.x[reg - gpr_x0]);
break;
+ case gpr_w0:
+ case gpr_w1:
+ case gpr_w2:
+ case gpr_w3:
+ case gpr_w4:
+ case gpr_w5:
+ case gpr_w6:
+ case gpr_w7:
+ case gpr_w8:
+ case gpr_w9:
+ case gpr_w10:
+ case gpr_w11:
+ case gpr_w12:
+ case gpr_w13:
+ case gpr_w14:
+ case gpr_w15:
+ case gpr_w16:
+ case gpr_w17:
+ case gpr_w18:
+ case gpr_w19:
+ case gpr_w20:
+ case gpr_w21:
+ case gpr_w22:
+ case gpr_w23:
+ case gpr_w24:
+ case gpr_w25:
+ case gpr_w26:
+ case gpr_w27:
+ case gpr_w28: {
+ ProcessSP process_sp(m_thread.GetProcess());
+ if (process_sp.get()) {
+ DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
+ process_sp->GetAddressByteSize());
+ offset_t offset = 0;
+ uint64_t retval = regdata.GetMaxU64(&offset, 8);
+ uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
+ value.SetUInt32(retval_lower32);
+ }
+ } break;
+
case fpu_v0:
case fpu_v1:
case fpu_v2:
@@ -388,6 +430,88 @@ bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
endian::InlHostByteOrder());
break;
+ case fpu_s0:
+ case fpu_s1:
+ case fpu_s2:
+ case fpu_s3:
+ case fpu_s4:
+ case fpu_s5:
+ case fpu_s6:
+ case fpu_s7:
+ case fpu_s8:
+ case fpu_s9:
+ case fpu_s10:
+ case fpu_s11:
+ case fpu_s12:
+ case fpu_s13:
+ case fpu_s14:
+ case fpu_s15:
+ case fpu_s16:
+ case fpu_s17:
+ case fpu_s18:
+ case fpu_s19:
+ case fpu_s20:
+ case fpu_s21:
+ case fpu_s22:
+ case fpu_s23:
+ case fpu_s24:
+ case fpu_s25:
+ case fpu_s26:
+ case fpu_s27:
+ case fpu_s28:
+ case fpu_s29:
+ case fpu_s30:
+ case fpu_s31: {
+ ProcessSP process_sp(m_thread.GetProcess());
+ if (process_sp.get()) {
+ DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
+ process_sp->GetAddressByteSize());
+ offset_t offset = 0;
+ value.SetFloat(regdata.GetFloat(&offset));
+ }
+ } break;
+
+ case fpu_d0:
+ case fpu_d1:
+ case fpu_d2:
+ case fpu_d3:
+ case fpu_d4:
+ case fpu_d5:
+ case fpu_d6:
+ case fpu_d7:
+ case fpu_d8:
+ case fpu_d9:
+ case fpu_d10:
+ case fpu_d11:
+ case fpu_d12:
+ case fpu_d13:
+ case fpu_d14:
+ case fpu_d15:
+ case fpu_d16:
+ case fpu_d17:
+ case fpu_d18:
+ case fpu_d19:
+ case fpu_d20:
+ case fpu_d21:
+ case fpu_d22:
+ case fpu_d23:
+ case fpu_d24:
+ case fpu_d25:
+ case fpu_d26:
+ case fpu_d27:
+ case fpu_d28:
+ case fpu_d29:
+ case fpu_d30:
+ case fpu_d31: {
+ ProcessSP process_sp(m_thread.GetProcess());
+ if (process_sp.get()) {
+ DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(),
+ process_sp->GetAddressByteSize());
+ offset_t offset = 0;
+ value.SetDouble(regdata.GetDouble(&offset));
+ }
+ } break;
+
case fpu_fpsr:
value.SetUInt32(fpu.fpsr);
break;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp
index 123f7d93d93..7b1ffdc5e2e 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp
@@ -56,7 +56,7 @@ static const lldb_private::RegisterInfo *
GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::aarch64:
- return g_register_infos_arm64;
+ return g_register_infos_arm64_le;
default:
assert(false && "Unhandled target architecture.");
return nullptr;
@@ -67,8 +67,8 @@ static uint32_t
GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::aarch64:
- return static_cast<uint32_t>(sizeof(g_register_infos_arm64) /
- sizeof(g_register_infos_arm64[0]));
+ return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
+ sizeof(g_register_infos_arm64_le[0]));
default:
assert(false && "Unhandled target architecture.");
return 0;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp
index 5eb194e2ce1..d6222c17630 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp
@@ -60,7 +60,7 @@ static const lldb_private::RegisterInfo *
GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::aarch64:
- return g_register_infos_arm64;
+ return g_register_infos_arm64_le;
default:
assert(false && "Unhandled target architecture.");
return NULL;
@@ -71,8 +71,8 @@ static uint32_t
GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::aarch64:
- return static_cast<uint32_t>(sizeof(g_register_infos_arm64) /
- sizeof(g_register_infos_arm64[0]));
+ return static_cast<uint32_t>(sizeof(g_register_infos_arm64_le) /
+ sizeof(g_register_infos_arm64_le[0]));
default:
assert(false && "Unhandled target architecture.");
return 0;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
index 928e699643b..ab7638b3da7 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -50,6 +50,11 @@
#error DEFINE_DBG must be defined before including this header file
#endif
+// Offsets for a little-endian layout of the register context
+#define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0
+#define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0
+#define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0
+
enum {
gpr_x0 = 0,
gpr_x1,
@@ -90,6 +95,36 @@ enum {
gpr_pc = 32,
gpr_cpsr,
+ gpr_w0,
+ gpr_w1,
+ gpr_w2,
+ gpr_w3,
+ gpr_w4,
+ gpr_w5,
+ gpr_w6,
+ gpr_w7,
+ gpr_w8,
+ gpr_w9,
+ gpr_w10,
+ gpr_w11,
+ gpr_w12,
+ gpr_w13,
+ gpr_w14,
+ gpr_w15,
+ gpr_w16,
+ gpr_w17,
+ gpr_w18,
+ gpr_w19,
+ gpr_w20,
+ gpr_w21,
+ gpr_w22,
+ gpr_w23,
+ gpr_w24,
+ gpr_w25,
+ gpr_w26,
+ gpr_w27,
+ gpr_w28,
+
fpu_v0,
fpu_v1,
fpu_v2,
@@ -123,6 +158,72 @@ enum {
fpu_v30,
fpu_v31,
+ fpu_s0,
+ fpu_s1,
+ fpu_s2,
+ fpu_s3,
+ fpu_s4,
+ fpu_s5,
+ fpu_s6,
+ fpu_s7,
+ fpu_s8,
+ fpu_s9,
+ fpu_s10,
+ fpu_s11,
+ fpu_s12,
+ fpu_s13,
+ fpu_s14,
+ fpu_s15,
+ fpu_s16,
+ fpu_s17,
+ fpu_s18,
+ fpu_s19,
+ fpu_s20,
+ fpu_s21,
+ fpu_s22,
+ fpu_s23,
+ fpu_s24,
+ fpu_s25,
+ fpu_s26,
+ fpu_s27,
+ fpu_s28,
+ fpu_s29,
+ fpu_s30,
+ fpu_s31,
+
+ fpu_d0,
+ fpu_d1,
+ fpu_d2,
+ fpu_d3,
+ fpu_d4,
+ fpu_d5,
+ fpu_d6,
+ fpu_d7,
+ fpu_d8,
+ fpu_d9,
+ fpu_d10,
+ fpu_d11,
+ fpu_d12,
+ fpu_d13,
+ fpu_d14,
+ fpu_d15,
+ fpu_d16,
+ fpu_d17,
+ fpu_d18,
+ fpu_d19,
+ fpu_d20,
+ fpu_d21,
+ fpu_d22,
+ fpu_d23,
+ fpu_d24,
+ fpu_d25,
+ fpu_d26,
+ fpu_d27,
+ fpu_d28,
+ fpu_d29,
+ fpu_d30,
+ fpu_d31,
+
fpu_fpsr,
fpu_fpcr,
@@ -201,7 +302,166 @@ enum {
k_num_registers
};
-static lldb_private::RegisterInfo g_register_infos_arm64[] = {
+static uint32_t g_x0_contains[] = {gpr_w0, LLDB_INVALID_REGNUM};
+static uint32_t g_x1_contains[] = {gpr_w1, LLDB_INVALID_REGNUM};
+static uint32_t g_x2_contains[] = {gpr_w2, LLDB_INVALID_REGNUM};
+static uint32_t g_x3_contains[] = {gpr_w3, LLDB_INVALID_REGNUM};
+static uint32_t g_x4_contains[] = {gpr_w4, LLDB_INVALID_REGNUM};
+static uint32_t g_x5_contains[] = {gpr_w5, LLDB_INVALID_REGNUM};
+static uint32_t g_x6_contains[] = {gpr_w6, LLDB_INVALID_REGNUM};
+static uint32_t g_x7_contains[] = {gpr_w7, LLDB_INVALID_REGNUM};
+static uint32_t g_x8_contains[] = {gpr_w8, LLDB_INVALID_REGNUM};
+static uint32_t g_x9_contains[] = {gpr_w9, LLDB_INVALID_REGNUM};
+static uint32_t g_x10_contains[] = {gpr_w10, LLDB_INVALID_REGNUM};
+static uint32_t g_x11_contains[] = {gpr_w11, LLDB_INVALID_REGNUM};
+static uint32_t g_x12_contains[] = {gpr_w12, LLDB_INVALID_REGNUM};
+static uint32_t g_x13_contains[] = {gpr_w13, LLDB_INVALID_REGNUM};
+static uint32_t g_x14_contains[] = {gpr_w14, LLDB_INVALID_REGNUM};
+static uint32_t g_x15_contains[] = {gpr_w15, LLDB_INVALID_REGNUM};
+static uint32_t g_x16_contains[] = {gpr_w16, LLDB_INVALID_REGNUM};
+static uint32_t g_x17_contains[] = {gpr_w17, LLDB_INVALID_REGNUM};
+static uint32_t g_x18_contains[] = {gpr_w18, LLDB_INVALID_REGNUM};
+static uint32_t g_x19_contains[] = {gpr_w19, LLDB_INVALID_REGNUM};
+static uint32_t g_x20_contains[] = {gpr_w20, LLDB_INVALID_REGNUM};
+static uint32_t g_x21_contains[] = {gpr_w21, LLDB_INVALID_REGNUM};
+static uint32_t g_x22_contains[] = {gpr_w22, LLDB_INVALID_REGNUM};
+static uint32_t g_x23_contains[] = {gpr_w23, LLDB_INVALID_REGNUM};
+static uint32_t g_x24_contains[] = {gpr_w24, LLDB_INVALID_REGNUM};
+static uint32_t g_x25_contains[] = {gpr_w25, LLDB_INVALID_REGNUM};
+static uint32_t g_x26_contains[] = {gpr_w26, LLDB_INVALID_REGNUM};
+static uint32_t g_x27_contains[] = {gpr_w27, LLDB_INVALID_REGNUM};
+static uint32_t g_x28_contains[] = {gpr_w28, LLDB_INVALID_REGNUM};
+
+static uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM};
+static uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM};
+static uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM};
+static uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM};
+static uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM};
+static uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM};
+static uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM};
+static uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM};
+static uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM};
+static uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM};
+static uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM};
+static uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM};
+static uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM};
+static uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM};
+static uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM};
+static uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM};
+static uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM};
+static uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM};
+static uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM};
+static uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM};
+static uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM};
+static uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM};
+static uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM};
+static uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM};
+static uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM};
+static uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM};
+static uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM};
+static uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM};
+static uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM};
+
+static uint32_t g_v0_contains[] = {fpu_s0, fpu_d0, LLDB_INVALID_REGNUM};
+static uint32_t g_v1_contains[] = {fpu_s1, fpu_d1, LLDB_INVALID_REGNUM};
+static uint32_t g_v2_contains[] = {fpu_s2, fpu_d2, LLDB_INVALID_REGNUM};
+static uint32_t g_v3_contains[] = {fpu_s3, fpu_d3, LLDB_INVALID_REGNUM};
+static uint32_t g_v4_contains[] = {fpu_s4, fpu_d4, LLDB_INVALID_REGNUM};
+static uint32_t g_v5_contains[] = {fpu_s5, fpu_d5, LLDB_INVALID_REGNUM};
+static uint32_t g_v6_contains[] = {fpu_s6, fpu_d6, LLDB_INVALID_REGNUM};
+static uint32_t g_v7_contains[] = {fpu_s7, fpu_d7, LLDB_INVALID_REGNUM};
+static uint32_t g_v8_contains[] = {fpu_s8, fpu_d8, LLDB_INVALID_REGNUM};
+static uint32_t g_v9_contains[] = {fpu_s9, fpu_d9, LLDB_INVALID_REGNUM};
+static uint32_t g_v10_contains[] = {fpu_s10, fpu_d10, LLDB_INVALID_REGNUM};
+static uint32_t g_v11_contains[] = {fpu_s11, fpu_d11, LLDB_INVALID_REGNUM};
+static uint32_t g_v12_contains[] = {fpu_s12, fpu_d12, LLDB_INVALID_REGNUM};
+static uint32_t g_v13_contains[] = {fpu_s13, fpu_d13, LLDB_INVALID_REGNUM};
+static uint32_t g_v14_contains[] = {fpu_s14, fpu_d14, LLDB_INVALID_REGNUM};
+static uint32_t g_v15_contains[] = {fpu_s15, fpu_d15, LLDB_INVALID_REGNUM};
+static uint32_t g_v16_contains[] = {fpu_s16, fpu_d16, LLDB_INVALID_REGNUM};
+static uint32_t g_v17_contains[] = {fpu_s17, fpu_d17, LLDB_INVALID_REGNUM};
+static uint32_t g_v18_contains[] = {fpu_s18, fpu_d18, LLDB_INVALID_REGNUM};
+static uint32_t g_v19_contains[] = {fpu_s19, fpu_d19, LLDB_INVALID_REGNUM};
+static uint32_t g_v20_contains[] = {fpu_s20, fpu_d20, LLDB_INVALID_REGNUM};
+static uint32_t g_v21_contains[] = {fpu_s21, fpu_d21, LLDB_INVALID_REGNUM};
+static uint32_t g_v22_contains[] = {fpu_s22, fpu_d22, LLDB_INVALID_REGNUM};
+static uint32_t g_v23_contains[] = {fpu_s23, fpu_d23, LLDB_INVALID_REGNUM};
+static uint32_t g_v24_contains[] = {fpu_s24, fpu_d24, LLDB_INVALID_REGNUM};
+static uint32_t g_v25_contains[] = {fpu_s25, fpu_d25, LLDB_INVALID_REGNUM};
+static uint32_t g_v26_contains[] = {fpu_s26, fpu_d26, LLDB_INVALID_REGNUM};
+static uint32_t g_v27_contains[] = {fpu_s27, fpu_d27, LLDB_INVALID_REGNUM};
+static uint32_t g_v28_contains[] = {fpu_s28, fpu_d28, LLDB_INVALID_REGNUM};
+static uint32_t g_v29_contains[] = {fpu_s29, fpu_d29, LLDB_INVALID_REGNUM};
+static uint32_t g_v30_contains[] = {fpu_s30, fpu_d30, LLDB_INVALID_REGNUM};
+static uint32_t g_v31_contains[] = {fpu_s31, fpu_d31, LLDB_INVALID_REGNUM};
+
+static uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM};
+static uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM};
+static uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM};
+static uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM};
+static uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM};
+static uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM};
+static uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM};
+static uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM};
+static uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM};
+static uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM};
+static uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM};
+static uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM};
+static uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM};
+static uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM};
+static uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM};
+static uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM};
+static uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM};
+static uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM};
+static uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM};
+static uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM};
+static uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM};
+static uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM};
+static uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM};
+static uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM};
+static uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM};
+static uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM};
+static uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM};
+static uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM};
+static uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM};
+static uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM};
+static uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM};
+static uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM};
+
+static uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM};
+static uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM};
+static uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM};
+static uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM};
+static uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM};
+static uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM};
+static uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM};
+static uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM};
+static uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM};
+static uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM};
+static uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM};
+static uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM};
+static uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM};
+static uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM};
+static uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM};
+static uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM};
+static uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM};
+static uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM};
+static uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM};
+static uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM};
+static uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM};
+static uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM};
+static uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM};
+static uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM};
+static uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM};
+static uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM};
+static uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM};
+static uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM};
+static uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM};
+static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM};
+static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
+static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
+
+static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
// General purpose registers
// NAME ALT SZ OFFSET ENCODING
// FORMAT EH_FRAME DWARF
@@ -219,7 +479,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x0, arm64_dwarf::x0, LLDB_REGNUM_GENERIC_ARG1,
LLDB_INVALID_REGNUM, gpr_x0},
- nullptr,
+ g_x0_contains,
nullptr,
nullptr,
0},
@@ -231,7 +491,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x1, arm64_dwarf::x1, LLDB_REGNUM_GENERIC_ARG2,
LLDB_INVALID_REGNUM, gpr_x1},
- nullptr,
+ g_x1_contains,
nullptr,
nullptr,
0},
@@ -243,7 +503,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x2, arm64_dwarf::x2, LLDB_REGNUM_GENERIC_ARG3,
LLDB_INVALID_REGNUM, gpr_x2},
- nullptr,
+ g_x2_contains,
nullptr,
nullptr,
0},
@@ -255,7 +515,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x3, arm64_dwarf::x3, LLDB_REGNUM_GENERIC_ARG4,
LLDB_INVALID_REGNUM, gpr_x3},
- nullptr,
+ g_x3_contains,
nullptr,
nullptr,
0},
@@ -267,7 +527,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x4, arm64_dwarf::x4, LLDB_REGNUM_GENERIC_ARG5,
LLDB_INVALID_REGNUM, gpr_x4},
- nullptr,
+ g_x4_contains,
nullptr,
nullptr,
0},
@@ -279,7 +539,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x5, arm64_dwarf::x5, LLDB_REGNUM_GENERIC_ARG6,
LLDB_INVALID_REGNUM, gpr_x5},
- nullptr,
+ g_x5_contains,
nullptr,
nullptr,
0},
@@ -291,7 +551,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x6, arm64_dwarf::x6, LLDB_REGNUM_GENERIC_ARG7,
LLDB_INVALID_REGNUM, gpr_x6},
- nullptr,
+ g_x6_contains,
nullptr,
nullptr,
0},
@@ -303,7 +563,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x7, arm64_dwarf::x7, LLDB_REGNUM_GENERIC_ARG8,
LLDB_INVALID_REGNUM, gpr_x7},
- nullptr,
+ g_x7_contains,
nullptr,
nullptr,
0},
@@ -315,7 +575,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x8, arm64_dwarf::x8, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x8},
- nullptr,
+ g_x8_contains,
nullptr,
nullptr,
0},
@@ -327,7 +587,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x9, arm64_dwarf::x9, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x9},
- nullptr,
+ g_x9_contains,
nullptr,
nullptr,
0},
@@ -339,7 +599,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x10, arm64_dwarf::x10, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x10},
- nullptr,
+ g_x10_contains,
nullptr,
nullptr,
0},
@@ -351,7 +611,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x11, arm64_dwarf::x11, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x11},
- nullptr,
+ g_x11_contains,
nullptr,
nullptr,
0},
@@ -363,7 +623,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x12, arm64_dwarf::x12, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x12},
- nullptr,
+ g_x12_contains,
nullptr,
nullptr,
0},
@@ -375,7 +635,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x13, arm64_dwarf::x13, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x13},
- nullptr,
+ g_x13_contains,
nullptr,
nullptr,
0},
@@ -387,7 +647,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x14, arm64_dwarf::x14, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x14},
- nullptr,
+ g_x14_contains,
nullptr,
nullptr,
0},
@@ -399,7 +659,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x15, arm64_dwarf::x15, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x15},
- nullptr,
+ g_x15_contains,
nullptr,
nullptr,
0},
@@ -411,7 +671,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x16, arm64_dwarf::x16, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x16},
- nullptr,
+ g_x16_contains,
nullptr,
nullptr,
0},
@@ -423,7 +683,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x17, arm64_dwarf::x17, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x17},
- nullptr,
+ g_x17_contains,
nullptr,
nullptr,
0},
@@ -435,7 +695,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x18, arm64_dwarf::x18, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x18},
- nullptr,
+ g_x18_contains,
nullptr,
nullptr,
0},
@@ -447,7 +707,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x19, arm64_dwarf::x19, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x19},
- nullptr,
+ g_x19_contains,
nullptr,
nullptr,
0},
@@ -459,7 +719,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x20, arm64_dwarf::x20, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x20},
- nullptr,
+ g_x20_contains,
nullptr,
nullptr,
0},
@@ -471,7 +731,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x21, arm64_dwarf::x21, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x21},
- nullptr,
+ g_x21_contains,
nullptr,
nullptr,
0},
@@ -483,7 +743,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x22, arm64_dwarf::x22, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x22},
- nullptr,
+ g_x22_contains,
nullptr,
nullptr,
0},
@@ -495,7 +755,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x23, arm64_dwarf::x23, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x23},
- nullptr,
+ g_x23_contains,
nullptr,
nullptr,
0},
@@ -507,7 +767,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x24, arm64_dwarf::x24, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x24},
- nullptr,
+ g_x24_contains,
nullptr,
nullptr,
0},
@@ -519,7 +779,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x25, arm64_dwarf::x25, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x25},
- nullptr,
+ g_x25_contains,
nullptr,
nullptr,
0},
@@ -531,7 +791,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x26, arm64_dwarf::x26, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x26},
- nullptr,
+ g_x26_contains,
nullptr,
nullptr,
0},
@@ -543,7 +803,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x27, arm64_dwarf::x27, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x27},
- nullptr,
+ g_x27_contains,
nullptr,
nullptr,
0},
@@ -555,7 +815,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatHex,
{arm64_ehframe::x28, arm64_dwarf::x28, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, gpr_x28},
- nullptr,
+ g_x28_contains,
nullptr,
nullptr,
0},
@@ -622,6 +882,355 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
nullptr,
0},
+ {"w0",
+ nullptr,
+ 4,
+ GPR_OFFSET(0) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w0},
+ nullptr,
+ g_w0_invalidates,
+ nullptr,
+ 0},
+ {"w1",
+ nullptr,
+ 4,
+ GPR_OFFSET(1) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w1},
+ nullptr,
+ g_w1_invalidates,
+ nullptr,
+ 0},
+ {"w2",
+ nullptr,
+ 4,
+ GPR_OFFSET(2) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w2},
+ nullptr,
+ g_w2_invalidates,
+ nullptr,
+ 0},
+ {"w3",
+ nullptr,
+ 4,
+ GPR_OFFSET(3) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w3},
+ nullptr,
+ g_w3_invalidates,
+ nullptr,
+ 0},
+ {"w4",
+ nullptr,
+ 4,
+ GPR_OFFSET(4) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w4},
+ nullptr,
+ g_w4_invalidates,
+ nullptr,
+ 0},
+ {"w5",
+ nullptr,
+ 4,
+ GPR_OFFSET(5) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w5},
+ nullptr,
+ g_w5_invalidates,
+ nullptr,
+ 0},
+ {"w6",
+ nullptr,
+ 4,
+ GPR_OFFSET(6) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w6},
+ nullptr,
+ g_w6_invalidates,
+ nullptr,
+ 0},
+ {"w7",
+ nullptr,
+ 4,
+ GPR_OFFSET(7) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w7},
+ nullptr,
+ g_w7_invalidates,
+ nullptr,
+ 0},
+ {"w8",
+ nullptr,
+ 4,
+ GPR_OFFSET(8) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w8},
+ nullptr,
+ g_w8_invalidates,
+ nullptr,
+ 0},
+ {"w9",
+ nullptr,
+ 4,
+ GPR_OFFSET(9) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w9},
+ nullptr,
+ g_w9_invalidates,
+ nullptr,
+ 0},
+ {"w10",
+ nullptr,
+ 4,
+ GPR_OFFSET(10) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w10},
+ nullptr,
+ g_w10_invalidates,
+ nullptr,
+ 0},
+ {"w11",
+ nullptr,
+ 4,
+ GPR_OFFSET(11) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w11},
+ nullptr,
+ g_w11_invalidates,
+ nullptr,
+ 0},
+ {"w12",
+ nullptr,
+ 4,
+ GPR_OFFSET(12) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w12},
+ nullptr,
+ g_w12_invalidates,
+ nullptr,
+ 0},
+ {"w13",
+ nullptr,
+ 4,
+ GPR_OFFSET(13) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w13},
+ nullptr,
+ g_w13_invalidates,
+ nullptr,
+ 0},
+ {"w14",
+ nullptr,
+ 4,
+ GPR_OFFSET(14) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w14},
+ nullptr,
+ g_w14_invalidates,
+ nullptr,
+ 0},
+ {"w15",
+ nullptr,
+ 4,
+ GPR_OFFSET(15) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w15},
+ nullptr,
+ g_w15_invalidates,
+ nullptr,
+ 0},
+ {"w16",
+ nullptr,
+ 4,
+ GPR_OFFSET(16) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w16},
+ nullptr,
+ g_w16_invalidates,
+ nullptr,
+ 0},
+ {"w17",
+ nullptr,
+ 4,
+ GPR_OFFSET(17) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w17},
+ nullptr,
+ g_w17_invalidates,
+ nullptr,
+ 0},
+ {"w18",
+ nullptr,
+ 4,
+ GPR_OFFSET(18) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w18},
+ nullptr,
+ g_w18_invalidates,
+ nullptr,
+ 0},
+ {"w19",
+ nullptr,
+ 4,
+ GPR_OFFSET(19) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w19},
+ nullptr,
+ g_w19_invalidates,
+ nullptr,
+ 0},
+ {"w20",
+ nullptr,
+ 4,
+ GPR_OFFSET(20) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w20},
+ nullptr,
+ g_w20_invalidates,
+ nullptr,
+ 0},
+ {"w21",
+ nullptr,
+ 4,
+ GPR_OFFSET(21) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w21},
+ nullptr,
+ g_w21_invalidates,
+ nullptr,
+ 0},
+ {"w22",
+ nullptr,
+ 4,
+ GPR_OFFSET(22) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w22},
+ nullptr,
+ g_w22_invalidates,
+ nullptr,
+ 0},
+ {"w23",
+ nullptr,
+ 4,
+ GPR_OFFSET(23) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w23},
+ nullptr,
+ g_w23_invalidates,
+ nullptr,
+ 0},
+ {"w24",
+ nullptr,
+ 4,
+ GPR_OFFSET(24) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w24},
+ nullptr,
+ g_w24_invalidates,
+ nullptr,
+ 0},
+ {"w25",
+ nullptr,
+ 4,
+ GPR_OFFSET(25) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w25},
+ nullptr,
+ g_w25_invalidates,
+ nullptr,
+ 0},
+ {"w26",
+ nullptr,
+ 4,
+ GPR_OFFSET(26) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w26},
+ nullptr,
+ g_w26_invalidates,
+ nullptr,
+ 0},
+ {"w27",
+ nullptr,
+ 4,
+ GPR_OFFSET(27) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w27},
+ nullptr,
+ g_w27_invalidates,
+ nullptr,
+ 0},
+ {"w28",
+ nullptr,
+ 4,
+ GPR_OFFSET(28) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingUint,
+ lldb::eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, gpr_w28},
+ nullptr,
+ g_w28_invalidates,
+ nullptr,
+ 0},
+
{"v0",
nullptr,
16,
@@ -630,7 +1239,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v0, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v0},
- nullptr,
+ g_v0_contains,
nullptr,
nullptr,
0},
@@ -642,7 +1251,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v1, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v1},
- nullptr,
+ g_v1_contains,
nullptr,
nullptr,
0},
@@ -654,7 +1263,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v2, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v2},
- nullptr,
+ g_v2_contains,
nullptr,
nullptr,
0},
@@ -666,7 +1275,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v3, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v3},
- nullptr,
+ g_v3_contains,
nullptr,
nullptr,
0},
@@ -678,7 +1287,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v4, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v4},
- nullptr,
+ g_v4_contains,
nullptr,
nullptr,
0},
@@ -690,7 +1299,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v5, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v5},
- nullptr,
+ g_v5_contains,
nullptr,
nullptr,
0},
@@ -702,7 +1311,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v6, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v6},
- nullptr,
+ g_v6_contains,
nullptr,
nullptr,
0},
@@ -714,7 +1323,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v7, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v7},
- nullptr,
+ g_v7_contains,
nullptr,
nullptr,
0},
@@ -726,7 +1335,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v8, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v8},
- nullptr,
+ g_v8_contains,
nullptr,
nullptr,
0},
@@ -738,7 +1347,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v9, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v9},
- nullptr,
+ g_v9_contains,
nullptr,
nullptr,
0},
@@ -750,7 +1359,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v10, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v10},
- nullptr,
+ g_v10_contains,
nullptr,
nullptr,
0},
@@ -762,7 +1371,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v11, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v11},
- nullptr,
+ g_v11_contains,
nullptr,
nullptr,
0},
@@ -774,7 +1383,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v12, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v12},
- nullptr,
+ g_v12_contains,
nullptr,
nullptr,
0},
@@ -786,7 +1395,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v13, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v13},
- nullptr,
+ g_v13_contains,
nullptr,
nullptr,
0},
@@ -798,7 +1407,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v14, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v14},
- nullptr,
+ g_v14_contains,
nullptr,
nullptr,
0},
@@ -810,7 +1419,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v15, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v15},
- nullptr,
+ g_v15_contains,
nullptr,
nullptr,
0},
@@ -822,7 +1431,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v16, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v16},
- nullptr,
+ g_v16_contains,
nullptr,
nullptr,
0},
@@ -834,7 +1443,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v17, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v17},
- nullptr,
+ g_v17_contains,
nullptr,
nullptr,
0},
@@ -846,7 +1455,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v18, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v18},
- nullptr,
+ g_v18_contains,
nullptr,
nullptr,
0},
@@ -858,7 +1467,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v19, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v19},
- nullptr,
+ g_v19_contains,
nullptr,
nullptr,
0},
@@ -870,7 +1479,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v20, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v20},
- nullptr,
+ g_v20_contains,
nullptr,
nullptr,
0},
@@ -882,7 +1491,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v21, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v21},
- nullptr,
+ g_v21_contains,
nullptr,
nullptr,
0},
@@ -894,7 +1503,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v22, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v22},
- nullptr,
+ g_v22_contains,
nullptr,
nullptr,
0},
@@ -906,7 +1515,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v23, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v23},
- nullptr,
+ g_v23_contains,
nullptr,
nullptr,
0},
@@ -918,7 +1527,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v24, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v24},
- nullptr,
+ g_v24_contains,
nullptr,
nullptr,
0},
@@ -930,7 +1539,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v25, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v25},
- nullptr,
+ g_v25_contains,
nullptr,
nullptr,
0},
@@ -942,7 +1551,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v26, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v26},
- nullptr,
+ g_v26_contains,
nullptr,
nullptr,
0},
@@ -954,7 +1563,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v27, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v27},
- nullptr,
+ g_v27_contains,
nullptr,
nullptr,
0},
@@ -966,7 +1575,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v28, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v28},
- nullptr,
+ g_v28_contains,
nullptr,
nullptr,
0},
@@ -978,7 +1587,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v29, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v29},
- nullptr,
+ g_v29_contains,
nullptr,
nullptr,
0},
@@ -990,7 +1599,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v30, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v30},
- nullptr,
+ g_v30_contains,
nullptr,
nullptr,
0},
@@ -1002,8 +1611,778 @@ static lldb_private::RegisterInfo g_register_infos_arm64[] = {
lldb::eFormatVectorOfUInt8,
{LLDB_INVALID_REGNUM, arm64_dwarf::v31, LLDB_INVALID_REGNUM,
LLDB_INVALID_REGNUM, fpu_v31},
+ g_v31_contains,
+ nullptr,
+ nullptr,
+ 0},
+
+ {"s0",
+ nullptr,
+ 4,
+ FPU_OFFSET(0) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s0},
+ nullptr,
+ g_s0_invalidates,
+ nullptr,
+ 0},
+ {"s1",
nullptr,
+ 4,
+ FPU_OFFSET(1) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s1},
+ nullptr,
+ g_s1_invalidates,
+ nullptr,
+ 0},
+ {"s2",
+ nullptr,
+ 4,
+ FPU_OFFSET(2) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s2},
+ nullptr,
+ g_s2_invalidates,
+ nullptr,
+ 0},
+ {"s3",
+ nullptr,
+ 4,
+ FPU_OFFSET(3) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s3},
+ nullptr,
+ g_s3_invalidates,
+ nullptr,
+ 0},
+ {"s4",
+ nullptr,
+ 4,
+ FPU_OFFSET(4) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s4},
+ nullptr,
+ g_s4_invalidates,
+ nullptr,
+ 0},
+ {"s5",
+ nullptr,
+ 4,
+ FPU_OFFSET(5) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s5},
+ nullptr,
+ g_s5_invalidates,
+ nullptr,
+ 0},
+ {"s6",
+ nullptr,
+ 4,
+ FPU_OFFSET(6) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s6},
+ nullptr,
+ g_s6_invalidates,
+ nullptr,
+ 0},
+ {"s7",
+ nullptr,
+ 4,
+ FPU_OFFSET(7) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s7},
+ nullptr,
+ g_s7_invalidates,
+ nullptr,
+ 0},
+ {"s8",
+ nullptr,
+ 4,
+ FPU_OFFSET(8) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s8},
+ nullptr,
+ g_s8_invalidates,
+ nullptr,
+ 0},
+ {"s9",
+ nullptr,
+ 4,
+ FPU_OFFSET(9) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s9},
+ nullptr,
+ g_s9_invalidates,
+ nullptr,
+ 0},
+ {"s10",
+ nullptr,
+ 4,
+ FPU_OFFSET(10) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s10},
+ nullptr,
+ g_s10_invalidates,
+ nullptr,
+ 0},
+ {"s11",
+ nullptr,
+ 4,
+ FPU_OFFSET(11) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s11},
+ nullptr,
+ g_s11_invalidates,
+ nullptr,
+ 0},
+ {"s12",
+ nullptr,
+ 4,
+ FPU_OFFSET(12) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s12},
+ nullptr,
+ g_s12_invalidates,
+ nullptr,
+ 0},
+ {"s13",
+ nullptr,
+ 4,
+ FPU_OFFSET(13) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s13},
+ nullptr,
+ g_s13_invalidates,
+ nullptr,
+ 0},
+ {"s14",
+ nullptr,
+ 4,
+ FPU_OFFSET(14) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s14},
+ nullptr,
+ g_s14_invalidates,
+ nullptr,
+ 0},
+ {"s15",
+ nullptr,
+ 4,
+ FPU_OFFSET(15) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s15},
+ nullptr,
+ g_s15_invalidates,
+ nullptr,
+ 0},
+ {"s16",
+ nullptr,
+ 4,
+ FPU_OFFSET(16) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s16},
+ nullptr,
+ g_s16_invalidates,
+ nullptr,
+ 0},
+ {"s17",
+ nullptr,
+ 4,
+ FPU_OFFSET(17) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s17},
+ nullptr,
+ g_s17_invalidates,
+ nullptr,
+ 0},
+ {"s18",
+ nullptr,
+ 4,
+ FPU_OFFSET(18) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s18},
+ nullptr,
+ g_s18_invalidates,
+ nullptr,
+ 0},
+ {"s19",
+ nullptr,
+ 4,
+ FPU_OFFSET(19) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s19},
+ nullptr,
+ g_s19_invalidates,
+ nullptr,
+ 0},
+ {"s20",
+ nullptr,
+ 4,
+ FPU_OFFSET(20) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s20},
+ nullptr,
+ g_s20_invalidates,
+ nullptr,
+ 0},
+ {"s21",
+ nullptr,
+ 4,
+ FPU_OFFSET(21) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s21},
+ nullptr,
+ g_s21_invalidates,
+ nullptr,
+ 0},
+ {"s22",
+ nullptr,
+ 4,
+ FPU_OFFSET(22) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s22},
+ nullptr,
+ g_s22_invalidates,
+ nullptr,
+ 0},
+ {"s23",
+ nullptr,
+ 4,
+ FPU_OFFSET(23) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s23},
+ nullptr,
+ g_s23_invalidates,
+ nullptr,
+ 0},
+ {"s24",
+ nullptr,
+ 4,
+ FPU_OFFSET(24) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s24},
+ nullptr,
+ g_s24_invalidates,
+ nullptr,
+ 0},
+ {"s25",
+ nullptr,
+ 4,
+ FPU_OFFSET(25) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s25},
+ nullptr,
+ g_s25_invalidates,
+ nullptr,
+ 0},
+ {"s26",
+ nullptr,
+ 4,
+ FPU_OFFSET(26) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s26},
+ nullptr,
+ g_s26_invalidates,
+ nullptr,
+ 0},
+ {"s27",
+ nullptr,
+ 4,
+ FPU_OFFSET(27) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s27},
+ nullptr,
+ g_s27_invalidates,
+ nullptr,
+ 0},
+ {"s28",
+ nullptr,
+ 4,
+ FPU_OFFSET(28) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s28},
+ nullptr,
+ g_s28_invalidates,
+ nullptr,
+ 0},
+ {"s29",
+ nullptr,
+ 4,
+ FPU_OFFSET(29) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s29},
+ nullptr,
+ g_s29_invalidates,
+ nullptr,
+ 0},
+ {"s30",
+ nullptr,
+ 4,
+ FPU_OFFSET(30) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s30},
+ nullptr,
+ g_s30_invalidates,
+ nullptr,
+ 0},
+ {"s31",
+ nullptr,
+ 4,
+ FPU_OFFSET(31) + FPU_S_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_s31},
+ nullptr,
+ g_s31_invalidates,
+ nullptr,
+ 0},
+
+ {"d0",
+ nullptr,
+ 8,
+ FPU_OFFSET(0) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d0},
+ nullptr,
+ g_d0_invalidates,
+ nullptr,
+ 0},
+ {"d1",
+ nullptr,
+ 8,
+ FPU_OFFSET(1) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d1},
+ nullptr,
+ g_d1_invalidates,
+ nullptr,
+ 0},
+ {"d2",
+ nullptr,
+ 8,
+ FPU_OFFSET(2) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d2},
+ nullptr,
+ g_d2_invalidates,
+ nullptr,
+ 0},
+ {"d3",
+ nullptr,
+ 8,
+ FPU_OFFSET(3) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d3},
+ nullptr,
+ g_d3_invalidates,
+ nullptr,
+ 0},
+ {"d4",
+ nullptr,
+ 8,
+ FPU_OFFSET(4) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d4},
+ nullptr,
+ g_d4_invalidates,
+ nullptr,
+ 0},
+ {"d5",
+ nullptr,
+ 8,
+ FPU_OFFSET(5) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d5},
+ nullptr,
+ g_d5_invalidates,
+ nullptr,
+ 0},
+ {"d6",
+ nullptr,
+ 8,
+ FPU_OFFSET(6) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d6},
+ nullptr,
+ g_d6_invalidates,
+ nullptr,
+ 0},
+ {"d7",
+ nullptr,
+ 8,
+ FPU_OFFSET(7) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d7},
+ nullptr,
+ g_d7_invalidates,
+ nullptr,
+ 0},
+ {"d8",
+ nullptr,
+ 8,
+ FPU_OFFSET(8) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d8},
+ nullptr,
+ g_d8_invalidates,
+ nullptr,
+ 0},
+ {"d9",
+ nullptr,
+ 8,
+ FPU_OFFSET(9) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d9},
+ nullptr,
+ g_d9_invalidates,
+ nullptr,
+ 0},
+ {"d10",
+ nullptr,
+ 8,
+ FPU_OFFSET(10) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d10},
+ nullptr,
+ g_d10_invalidates,
+ nullptr,
+ 0},
+ {"d11",
+ nullptr,
+ 8,
+ FPU_OFFSET(11) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d11},
+ nullptr,
+ g_d11_invalidates,
+ nullptr,
+ 0},
+ {"d12",
+ nullptr,
+ 8,
+ FPU_OFFSET(12) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d12},
+ nullptr,
+ g_d12_invalidates,
+ nullptr,
+ 0},
+ {"d13",
+ nullptr,
+ 8,
+ FPU_OFFSET(13) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d13},
+ nullptr,
+ g_d13_invalidates,
+ nullptr,
+ 0},
+ {"d14",
+ nullptr,
+ 8,
+ FPU_OFFSET(14) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d14},
+ nullptr,
+ g_d14_invalidates,
+ nullptr,
+ 0},
+ {"d15",
+ nullptr,
+ 8,
+ FPU_OFFSET(15) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d15},
+ nullptr,
+ g_d15_invalidates,
+ nullptr,
+ 0},
+ {"d16",
+ nullptr,
+ 8,
+ FPU_OFFSET(16) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d16},
+ nullptr,
+ g_d16_invalidates,
+ nullptr,
+ 0},
+ {"d17",
+ nullptr,
+ 8,
+ FPU_OFFSET(17) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d17},
+ nullptr,
+ g_d17_invalidates,
+ nullptr,
+ 0},
+ {"d18",
+ nullptr,
+ 8,
+ FPU_OFFSET(18) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d18},
+ nullptr,
+ g_d18_invalidates,
+ nullptr,
+ 0},
+ {"d19",
+ nullptr,
+ 8,
+ FPU_OFFSET(19) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d19},
+ nullptr,
+ g_d19_invalidates,
+ nullptr,
+ 0},
+ {"d20",
+ nullptr,
+ 8,
+ FPU_OFFSET(20) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d20},
+ nullptr,
+ g_d20_invalidates,
+ nullptr,
+ 0},
+ {"d21",
+ nullptr,
+ 8,
+ FPU_OFFSET(21) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d21},
+ nullptr,
+ g_d21_invalidates,
+ nullptr,
+ 0},
+ {"d22",
+ nullptr,
+ 8,
+ FPU_OFFSET(22) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d22},
+ nullptr,
+ g_d22_invalidates,
+ nullptr,
+ 0},
+ {"d23",
+ nullptr,
+ 8,
+ FPU_OFFSET(23) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d23},
+ nullptr,
+ g_d23_invalidates,
+ nullptr,
+ 0},
+ {"d24",
+ nullptr,
+ 8,
+ FPU_OFFSET(24) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d24},
+ nullptr,
+ g_d24_invalidates,
+ nullptr,
+ 0},
+ {"d25",
+ nullptr,
+ 8,
+ FPU_OFFSET(25) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d25},
+ nullptr,
+ g_d25_invalidates,
+ nullptr,
+ 0},
+ {"d26",
+ nullptr,
+ 8,
+ FPU_OFFSET(26) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d26},
+ nullptr,
+ g_d26_invalidates,
+ nullptr,
+ 0},
+ {"d27",
+ nullptr,
+ 8,
+ FPU_OFFSET(27) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d27},
+ nullptr,
+ g_d27_invalidates,
+ nullptr,
+ 0},
+ {"d28",
+ nullptr,
+ 8,
+ FPU_OFFSET(28) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d28},
+ nullptr,
+ g_d28_invalidates,
+ nullptr,
+ 0},
+ {"d29",
+ nullptr,
+ 8,
+ FPU_OFFSET(29) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d29},
+ nullptr,
+ g_d29_invalidates,
+ nullptr,
+ 0},
+ {"d30",
+ nullptr,
+ 8,
+ FPU_OFFSET(30) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d30},
+ nullptr,
+ g_d30_invalidates,
+ nullptr,
+ 0},
+ {"d31",
+ nullptr,
+ 8,
+ FPU_OFFSET(31) + FPU_D_PSEUDO_REG_ENDIAN_OFFSET,
+ lldb::eEncodingIEEE754,
+ lldb::eFormatFloat,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, fpu_d31},
nullptr,
+ g_d31_invalidates,
nullptr,
0},
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