diff options
| -rw-r--r-- | libcxx/utils/google-benchmark/README.LLVM | 6 | ||||
| -rw-r--r-- | libcxx/utils/google-benchmark/src/cycleclock.h | 15 | ||||
| -rw-r--r-- | llvm/utils/benchmark/README.LLVM | 2 | ||||
| -rw-r--r-- | llvm/utils/benchmark/src/cycleclock.h | 15 |
4 files changed, 38 insertions, 0 deletions
diff --git a/libcxx/utils/google-benchmark/README.LLVM b/libcxx/utils/google-benchmark/README.LLVM index e51e2571bf6..6b81ddf873a 100644 --- a/libcxx/utils/google-benchmark/README.LLVM +++ b/libcxx/utils/google-benchmark/README.LLVM @@ -4,3 +4,9 @@ LLVM notes This directory contains the Google Benchmark source code with some unnecessary files removed. Note that this directory is under a different license than libc++. + +Changes: +* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2 + is applied on top of + https://github.com/google/benchmark/commit/4528c76b718acc9b57956f63069c699ae21edcab + to add RISC-V timer support. diff --git a/libcxx/utils/google-benchmark/src/cycleclock.h b/libcxx/utils/google-benchmark/src/cycleclock.h index f5e37b011b9..d5d62c4c7fe 100644 --- a/libcxx/utils/google-benchmark/src/cycleclock.h +++ b/libcxx/utils/google-benchmark/src/cycleclock.h @@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() { uint64_t tsc; asm("stck %0" : "=Q"(tsc) : : "cc"); return tsc; +#elif defined(__riscv) // RISC-V + // Use RDCYCLE (and RDCYCLEH on riscv32) +#if __riscv_xlen == 32 + uint64_t cycles_low, cycles_hi0, cycles_hi1; + asm("rdcycleh %0" : "=r"(cycles_hi0)); + asm("rdcycle %0" : "=r"(cycles_lo)); + asm("rdcycleh %0" : "=r"(cycles_hi1)); + // This matches the PowerPC overflow detection, above + cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1); + return (cycles_hi1 << 32) | cycles_lo; +#else + uint64_t cycles; + asm("rdcycle %0" : "=r"(cycles)); + return cycles; +#endif #else // The soft failover to a generic implementation is automatic only for ARM. // For other platforms the developer is expected to make an attempt to create diff --git a/llvm/utils/benchmark/README.LLVM b/llvm/utils/benchmark/README.LLVM index c493ff4f5c6..d2aa87e86e7 100644 --- a/llvm/utils/benchmark/README.LLVM +++ b/llvm/utils/benchmark/README.LLVM @@ -23,3 +23,5 @@ Changes: is applied to disable exceptions in Microsoft STL when exceptions are disabled * Disabled CMake get_git_version as it is meaningless for this in-tree build, and hardcoded a null version +* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2 + is applied on top of v1.4.1 to add RISC-V timer support. diff --git a/llvm/utils/benchmark/src/cycleclock.h b/llvm/utils/benchmark/src/cycleclock.h index e1f18cc64d2..7b54b253037 100644 --- a/llvm/utils/benchmark/src/cycleclock.h +++ b/llvm/utils/benchmark/src/cycleclock.h @@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() { uint64_t tsc; asm("stck %0" : "=Q" (tsc) : : "cc"); return tsc; +#elif defined(__riscv) // RISC-V + // Use RDCYCLE (and RDCYCLEH on riscv32) +#if __riscv_xlen == 32 + uint64_t cycles_low, cycles_hi0, cycles_hi1; + asm("rdcycleh %0" : "=r"(cycles_hi0)); + asm("rdcycle %0" : "=r"(cycles_lo)); + asm("rdcycleh %0" : "=r"(cycles_hi1)); + // This matches the PowerPC overflow detection, above + cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1); + return (cycles_hi1 << 32) | cycles_lo; +#else + uint64_t cycles; + asm("rdcycle %0" : "=r"(cycles)); + return cycles; +#endif #else // The soft failover to a generic implementation is automatic only for ARM. // For other platforms the developer is expected to make an attempt to create |
