diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/half.ll | 12 |
2 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 8468a83f273..02db24e13ce 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1229,6 +1229,7 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC, if (VT == MVT::f16) { LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); + VT = MVT::f32; } return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); } diff --git a/llvm/test/CodeGen/AArch64/half.ll b/llvm/test/CodeGen/AArch64/half.ll index d4cbbc918a8..154d85c9bb6 100644 --- a/llvm/test/CodeGen/AArch64/half.ll +++ b/llvm/test/CodeGen/AArch64/half.ll @@ -81,3 +81,15 @@ define void @test_trunc64(double %in, half* %addr) { store half %val16, half* %addr ret void } + +define i16 @test_fccmp(i1 %a) { +;CHECK-LABEL: test_fccmp: +;CHECK: fcmp + %cmp0 = fcmp ogt half 0xH3333, undef + %cmp1 = fcmp ogt half 0xH2222, undef + %x = select i1 %cmp0, i16 0, i16 undef + %or = or i1 %cmp1, %cmp0 + %y = select i1 %or, i16 4, i16 undef + %r = add i16 %x, %y + ret i16 %r +} |
