diff options
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll | 36 |
2 files changed, 23 insertions, 16 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 2bcb5559101..353c4a22fe6 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -258,7 +258,8 @@ bool IRTranslator::translateSwitch(const User &U, MachineBasicBlock *FalseMBB = MF->CreateMachineBasicBlock(SwInst.getParent()); - MF->push_back(FalseMBB); + // Insert the comparison blocks one after the other. + MF->insert(std::next(CurMBB.getIterator()), FalseMBB); MIRBuilder.buildBr(*FalseMBB); CurMBB.addSuccessor(FalseMBB); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index d4de7280320..88cb2554691 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -117,7 +117,17 @@ false: ; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]] ; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]] ; -; CHECK: [[BB_DEFAULT:bb.[0-9]+.default]]: +; CHECK: [[BB_NOTCASE100_CHECKNEXT]]: +; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) +; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0 +; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]] +; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]] +; +; CHECK: [[BB_NOTCASE200_CHECKNEXT]]: +; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000) +; CHECK: G_BR %[[BB_DEFAULT]] +; +; CHECK: [[BB_DEFAULT]]: ; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000) ; CHECK: %[[regretdefault:[0-9]+]](s32) = G_ADD %0, %[[reg0]] ; CHECK: G_BR %[[BB_RET]] @@ -127,7 +137,7 @@ false: ; CHECK: %[[regretc100:[0-9]+]](s32) = G_ADD %0, %[[reg1]] ; CHECK: G_BR %[[BB_RET]] ; -; CHECK: [[BB_CASE200:bb.[0-9]+.case200]]: +; CHECK: [[BB_CASE200]]: ; CHECK-NEXT: successors: %[[BB_RET]](0x80000000) ; CHECK: %[[regretc200:[0-9]+]](s32) = G_ADD %0, %[[reg2]] ; CHECK: G_BR %[[BB_RET]] @@ -137,15 +147,6 @@ false: ; CHECK: %w0 = COPY %[[regret]](s32) ; CHECK: RET_ReallyLR implicit %w0 ; -; CHECK: [[BB_NOTCASE100_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_CASE200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000) -; CHECK: %[[regicmp200:[0-9]+]](s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0 -; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]] -; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]] -; -; CHECK: [[BB_NOTCASE200_CHECKNEXT]]: -; CHECK-NEXT: successors: %[[BB_DEFAULT]](0x80000000) -; CHECK: G_BR %[[BB_DEFAULT]] define i32 @switch(i32 %argc) { entry: switch i32 %argc, label %default [ @@ -174,12 +175,17 @@ return: ; %entry block is no longer a predecessor for the phi instruction. We need to ; use the correct lowered MachineBasicBlock instead. ; CHECK-LABEL: name: test_cfg_remap -; CHECK: [[PHI_BLOCK:bb.[0-9]+.phi.block]]: -; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32), - +; CHECK: {{bb.[0-9]+.entry}}: +; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000) +; CHECK: [[NOTCASE1_BLOCK]]: +; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000) ; CHECK: [[NOTCASE57_BLOCK]]: -; CHECK-NEXT: successors: %[[PHI_BLOCK]] +; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000) ; CHECK: G_BR %[[PHI_BLOCK]] +; +; CHECK: [[PHI_BLOCK]]: +; CHECK-NEXT: PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32), +; define i32 @test_cfg_remap(i32 %in) { entry: switch i32 %in, label %phi.block [i32 1, label %next |
