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-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 19615550aad..d45a8005756 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10895,8 +10895,8 @@ static SDValue getPTest(SelectionDAG &DAG, EVT VT, SDValue Pg, SDValue Op,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDLoc DL(Op);
- EVT OpVT = Op.getValueType();
- assert(OpVT.isScalableVector() && TLI.isTypeLegal(OpVT) &&
+ assert(Op.getValueType().isScalableVector() &&
+ TLI.isTypeLegal(Op.getValueType()) &&
"Expected legal scalable vector type!");
// Ensure target specific opcodes are using legal type.
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