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-rw-r--r--llvm/test/CodeGen/AArch64/signbit-shift.ll31
-rw-r--r--llvm/test/CodeGen/PowerPC/signbit-shift.ll39
-rw-r--r--llvm/test/CodeGen/X86/signbit-shift.ll34
3 files changed, 87 insertions, 17 deletions
diff --git a/llvm/test/CodeGen/AArch64/signbit-shift.ll b/llvm/test/CodeGen/AArch64/signbit-shift.ll
index c2f62c24026..b554ce15872 100644
--- a/llvm/test/CodeGen/AArch64/signbit-shift.ll
+++ b/llvm/test/CodeGen/AArch64/signbit-shift.ll
@@ -222,9 +222,30 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
ret <4 x i32> %r
}
-define i32 @sub_lshr(i32 %x) {
+define i32 @sub_lshr(i32 %x, i32 %y) {
; CHECK-LABEL: sub_lshr:
; CHECK: // %bb.0:
+; CHECK-NEXT: sub w0, w1, w0, lsr #31
+; CHECK-NEXT: ret
+ %sh = lshr i32 %x, 31
+ %r = sub i32 %y, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: sub_lshr_vec:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ushr v0.4s, v0.4s, #31
+; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> %y, %sh
+ ret <4 x i32> %r
+}
+
+define i32 @sub_const_op_lshr(i32 %x) {
+; CHECK-LABEL: sub_const_op_lshr:
+; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: sub w0, w8, w0, lsr #31
; CHECK-NEXT: ret
@@ -233,15 +254,15 @@ define i32 @sub_lshr(i32 %x) {
ret i32 %r
}
-define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
-; CHECK-LABEL: sub_lshr_vec_splat:
+define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
+; CHECK-LABEL: sub_const_op_lshr_vec:
; CHECK: // %bb.0:
; CHECK-NEXT: ushr v0.4s, v0.4s, #31
; CHECK-NEXT: movi v1.4s, #42
; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s
; CHECK-NEXT: ret
- %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
- %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
ret <4 x i32> %r
}
diff --git a/llvm/test/CodeGen/PowerPC/signbit-shift.ll b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
index d82fe842b03..75875878144 100644
--- a/llvm/test/CodeGen/PowerPC/signbit-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/signbit-shift.ll
@@ -240,10 +240,35 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
ret <4 x i32> %r
}
-define i32 @sub_lshr(i32 %x) {
+define i32 @sub_lshr(i32 %x, i32 %y) {
; CHECK-LABEL: sub_lshr:
; CHECK: # %bb.0:
; CHECK-NEXT: srwi 3, 3, 31
+; CHECK-NEXT: subf 3, 3, 4
+; CHECK-NEXT: blr
+ %sh = lshr i32 %x, 31
+ %r = sub i32 %y, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: sub_lshr_vec:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vspltisw 4, -16
+; CHECK-NEXT: vspltisw 5, 15
+; CHECK-NEXT: vsubuwm 4, 5, 4
+; CHECK-NEXT: vsrw 2, 2, 4
+; CHECK-NEXT: vsubuwm 2, 3, 2
+; CHECK-NEXT: blr
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> %y, %sh
+ ret <4 x i32> %r
+}
+
+define i32 @sub_const_op_lshr(i32 %x) {
+; CHECK-LABEL: sub_const_op_lshr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 43
; CHECK-NEXT: blr
%sh = lshr i32 %x, 31
@@ -251,20 +276,20 @@ define i32 @sub_lshr(i32 %x) {
ret i32 %r
}
-define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
-; CHECK-LABEL: sub_lshr_vec_splat:
+define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
+; CHECK-LABEL: sub_const_op_lshr_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: vspltisw 3, -16
; CHECK-NEXT: vspltisw 4, 15
-; CHECK-NEXT: addis 3, 2, .LCPI19_0@toc@ha
-; CHECK-NEXT: addi 3, 3, .LCPI19_0@toc@l
+; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha
+; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l
; CHECK-NEXT: vsubuwm 3, 4, 3
; CHECK-NEXT: vsrw 2, 2, 3
; CHECK-NEXT: lvx 3, 0, 3
; CHECK-NEXT: vsubuwm 2, 3, 2
; CHECK-NEXT: blr
- %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
- %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
ret <4 x i32> %r
}
diff --git a/llvm/test/CodeGen/X86/signbit-shift.ll b/llvm/test/CodeGen/X86/signbit-shift.ll
index 510bfe515ac..cee647931bc 100644
--- a/llvm/test/CodeGen/X86/signbit-shift.ll
+++ b/llvm/test/CodeGen/X86/signbit-shift.ll
@@ -228,10 +228,34 @@ define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
ret <4 x i32> %r
}
-define i32 @sub_lshr(i32 %x) {
+define i32 @sub_lshr(i32 %x, i32 %y) {
; CHECK-LABEL: sub_lshr:
; CHECK: # %bb.0:
; CHECK-NEXT: shrl $31, %edi
+; CHECK-NEXT: subl %edi, %esi
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: retq
+ %sh = lshr i32 %x, 31
+ %r = sub i32 %y, %sh
+ ret i32 %r
+}
+
+define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: sub_lshr_vec:
+; CHECK: # %bb.0:
+; CHECK-NEXT: psrld $31, %xmm0
+; CHECK-NEXT: psubd %xmm0, %xmm1
+; CHECK-NEXT: movdqa %xmm1, %xmm0
+; CHECK-NEXT: retq
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> %y, %sh
+ ret <4 x i32> %r
+}
+
+define i32 @sub_const_op_lshr(i32 %x) {
+; CHECK-LABEL: sub_const_op_lshr:
+; CHECK: # %bb.0:
+; CHECK-NEXT: shrl $31, %edi
; CHECK-NEXT: xorl $43, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
@@ -240,16 +264,16 @@ define i32 @sub_lshr(i32 %x) {
ret i32 %r
}
-define <4 x i32> @sub_lshr_vec_splat(<4 x i32> %x) {
-; CHECK-LABEL: sub_lshr_vec_splat:
+define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {
+; CHECK-LABEL: sub_const_op_lshr_vec:
; CHECK: # %bb.0:
; CHECK-NEXT: psrld $31, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [42,42,42,42]
; CHECK-NEXT: psubd %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm1, %xmm0
; CHECK-NEXT: retq
- %e = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
- %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
+ %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+ %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh
ret <4 x i32> %r
}
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