diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse2-schedule.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/sse41-schedule.ll | 2 |
4 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 5ab140b1744..e1c621fe38d 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -9757,7 +9757,7 @@ multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode, OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(store (_.EltVT (trunc (OpNode (_.VT _.RC:$src1), imm:$src2))), addr:$dst)]>, - EVEX, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteShuffleLd]>; + EVEX, EVEX_CD8<_.EltSize, CD8VT1>, Sched<[WriteShuffleLd, WriteRMW]>; } multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> { @@ -9809,7 +9809,7 @@ multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _, [(store (extractelt (_.VT _.RC:$src1), imm:$src2),addr:$dst)]>, EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD, - Sched<[WriteShuffleLd]>; + Sched<[WriteShuffleLd, WriteRMW]>; } } diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index baf0a07d466..9d7ee71b43a 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -4261,14 +4261,14 @@ def VPEXTRWrr : Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), - imm:$src2))]>, PD, VEX, - Sched<[WriteShuffle]>; + imm:$src2))], IIC_SSE_PEXTRW>, + PD, VEX, Sched<[WriteShuffle]>; def PEXTRWrr : PDIi8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2), "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1), imm:$src2))], IIC_SSE_PEXTRW>, - Sched<[WriteShuffleLd, ReadAfterLd]>; + Sched<[WriteShuffle]>; // Insert let Predicates = [HasAVX, NoBWI] in @@ -5632,7 +5632,7 @@ multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> { (ins VR128:$src1, u8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - []>, Sched<[WriteShuffle]>, FoldGenData<NAME#ri>; + [], IIC_SSE_PEXTRW>, Sched<[WriteShuffle]>, FoldGenData<NAME#ri>; let hasSideEffects = 0, mayStore = 1, SchedRW = [WriteShuffleLd, WriteRMW] in diff --git a/llvm/test/CodeGen/X86/sse2-schedule.ll b/llvm/test/CodeGen/X86/sse2-schedule.ll index 4fbce3bab23..c51d19a7c28 100644 --- a/llvm/test/CodeGen/X86/sse2-schedule.ll +++ b/llvm/test/CodeGen/X86/sse2-schedule.ll @@ -5496,7 +5496,7 @@ define i16 @test_pextrw(<8 x i16> %a0) { ; ; SLM-LABEL: test_pextrw: ; SLM: # %bb.0: -; SLM-NEXT: pextrw $6, %xmm0, %eax # sched: [4:1.00] +; SLM-NEXT: pextrw $6, %xmm0, %eax # sched: [1:1.00] ; SLM-NEXT: # kill: def %ax killed %ax killed %eax ; SLM-NEXT: retq # sched: [4:1.00] ; diff --git a/llvm/test/CodeGen/X86/sse41-schedule.ll b/llvm/test/CodeGen/X86/sse41-schedule.ll index 5e05a365d18..33a042f92b0 100644 --- a/llvm/test/CodeGen/X86/sse41-schedule.ll +++ b/llvm/test/CodeGen/X86/sse41-schedule.ll @@ -1083,7 +1083,7 @@ define i32 @test_pextrw(<8 x i16> %a0, i16 *%a1) { ; ; SLM-LABEL: test_pextrw: ; SLM: # %bb.0: -; SLM-NEXT: pextrw $3, %xmm0, %eax # sched: [4:1.00] +; SLM-NEXT: pextrw $3, %xmm0, %eax # sched: [1:1.00] ; SLM-NEXT: pextrw $1, %xmm0, (%rdi) # sched: [4:2.00] ; SLM-NEXT: retq # sched: [4:1.00] ; |
