diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/sdivpow2.ll | 15 |
3 files changed, 17 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 46263020300..5972d4aad78 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -4515,9 +4515,8 @@ bool AArch64FastISel::selectSDiv(const Instruction *I) { return true; } - unsigned Pow2MinusOne = (1 << Lg2) - 1; - unsigned AddReg = emitAddSub_ri(/*UseAdd=*/true, VT, Src0Reg, - /*IsKill=*/false, Pow2MinusOne); + int64_t Pow2MinusOne = (1ULL << Lg2) - 1; + unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); if (!AddReg) return false; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 5cfd6645c65..4d51c4f21d2 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6822,7 +6822,7 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, SDValue N0 = N->getOperand(0); unsigned Lg2 = Divisor.countTrailingZeros(); SDValue Zero = DAG.getConstant(0, VT); - SDValue Pow2MinusOne = DAG.getConstant((1 << Lg2) - 1, VT); + SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT); // Add (N0 < 0) ? Pow2 - 1 : 0; SDValue CCVal; diff --git a/llvm/test/CodeGen/AArch64/sdivpow2.ll b/llvm/test/CodeGen/AArch64/sdivpow2.ll index 6dee06dbd65..6c02ea9a467 100644 --- a/llvm/test/CodeGen/AArch64/sdivpow2.ll +++ b/llvm/test/CodeGen/AArch64/sdivpow2.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s +; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-linux-gnu -fast-isel=1 -verify-machineinstrs < %s | FileCheck %s define i32 @test1(i32 %x) { ; CHECK-LABEL: test1 @@ -59,3 +60,15 @@ define i64 @test6(i64 %x) { %div = sdiv i64 %x, 64 ret i64 %div } + +define i64 @test7(i64 %x) { +; CHECK-LABEL: test7 +; CHECK: orr [[REG:x[0-9]+]], xzr, #0xffffffffffff +; CHECK: add x8, x0, [[REG]] +; CHECK: cmp x0, #0 +; CHECK: csel x8, x8, x0, lt +; CHECK: asr x0, x8, #48 + %div = sdiv i64 %x, 281474976710656 + ret i64 %div +} + |
