diff options
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/micromips-addu16.ll | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/micromips-subu16.ll | 18 |
4 files changed, 3 insertions, 42 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 19120202af7..e20df2f4e62 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -642,10 +642,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { LW_FM_MM<0xc>; /// Arithmetic Instructions (3-Operand, R-Type) - def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM_MM<0, 0x150>; - def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM_MM<0, 0x1d0>; + def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>; + def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>; def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>; def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>; def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index c33b349a955..f2fdff8ff7c 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1140,13 +1140,12 @@ def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>, ADDI_FM<0xe>; def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM; -let AdditionalPredicates = [NotInMicroMips] in { + /// Arithmetic Instructions (3-Operand, R-Type) def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, ADD_FM<0, 0x21>; def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, ADD_FM<0, 0x23>; -} let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; diff --git a/llvm/test/CodeGen/Mips/micromips-addu16.ll b/llvm/test/CodeGen/Mips/micromips-addu16.ll deleted file mode 100644 index adebaf03bcf..00000000000 --- a/llvm/test/CodeGen/Mips/micromips-addu16.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s | FileCheck %s - -define i32 @main() { -entry: - %retval = alloca i32, align 4 - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* %b, align 4 - %1 = load i32* %c, align 4 - %add = add nsw i32 %0, %1 - store i32 %add, i32* %a, align 4 - ret i32 0 -} - -; CHECK: addu16 diff --git a/llvm/test/CodeGen/Mips/micromips-subu16.ll b/llvm/test/CodeGen/Mips/micromips-subu16.ll deleted file mode 100644 index 4ca16ef7c61..00000000000 --- a/llvm/test/CodeGen/Mips/micromips-subu16.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s | FileCheck %s - -define i32 @main() { -entry: - %retval = alloca i32, align 4 - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32* %b, align 4 - %1 = load i32* %c, align 4 - %sub = sub nsw i32 %0, %1 - store i32 %sub, i32* %a, align 4 - ret i32 0 -} - -; CHECK: subu16 |
