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-rw-r--r--llvm/lib/CodeGen/MachineSink.cpp16
-rw-r--r--llvm/test/CodeGen/AArch64/fast-isel-machine-sink.ll27
2 files changed, 40 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 81aaca02a4d..0c29c76309e 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -736,9 +736,19 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) {
++MachineBasicBlock::iterator(DbgMI));
}
- // Conservatively, clear any kill flags, since it's possible that they are no
- // longer correct.
- MI->clearKillInfo();
+ // When sinking the instruction the live time of its operands can be extended
+ // bejond their original last use (marked with a kill flag). Conservatively
+ // clear the kill flag in all instructions that use the same operand
+ // registers.
+ for (auto &MO : MI->uses())
+ if (MO.isReg() && MO.isUse()) {
+ // Preserve the kill flag for this instruction.
+ bool IsKill = MO.isKill();
+ // Clear the kill flag in all instruction that use this operand.
+ MRI->clearKillFlags(MO.getReg());
+ // Restore the kill flag for only this instruction.
+ MO.setIsKill(IsKill);
+ }
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-machine-sink.ll b/llvm/test/CodeGen/AArch64/fast-isel-machine-sink.ll
new file mode 100644
index 00000000000..74d3e8dbad0
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fast-isel-machine-sink.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs < %s
+
+define void @test() {
+ %sext = shl i64 undef, 32
+ %1 = ashr exact i64 %sext, 32
+ %2 = icmp sgt i64 undef, %1
+ br i1 %2, label %3, label %.critedge1
+
+; <label>:3 ; preds = %0
+ %4 = getelementptr inbounds i32* undef, i64 %1
+ %5 = load i32* %4, align 4
+ br i1 undef, label %6, label %.critedge1
+
+; <label>:6 ; preds = %3
+ %7 = and i32 %5, 255
+ %8 = icmp eq i32 %7, 255
+ br i1 %8, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %.lr.ph, %6
+ br i1 undef, label %.lr.ph, label %.critedge1
+
+._crit_edge: ; preds = %6
+ ret void
+
+.critedge1: ; preds = %.lr.ph, %3, %0
+ ret void
+}
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