[Simplify] Add test case which we currently miss

llvm-svn: 307643

1 files changed, 110 insertions, 0 deletions

diff --git a/polly/test/Simplify/gemm___%bb3---%bb28.jscop b/polly/test/Simplify/gemm___%bb3---%bb28.jscop
new file mode 100644
index 00000000000..7fb352216ed
--- /dev/null
+++ b/polly/test/Simplify/gemm___%bb3---%bb28.jscop
@@ -0,0 +1,110 @@
+{
+   "arrays" : [
+      {
+         "name" : "MemRef_C",
+         "sizes" : [ "*", "1024" ],
+         "type" : "float"
+      },
+      {
+         "name" : "MemRef_A",
+         "sizes" : [ "*", "1024" ],
+         "type" : "float"
+      },
+      {
+         "name" : "MemRef_B",
+         "sizes" : [ "*", "1024" ],
+         "type" : "float"
+      }
+   ],
+   "context" : "{  :  }",
+   "name" : "%bb3---%bb28",
+   "statements" : [
+      {
+         "accesses" : [
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb8[i0, i1] -> MemRef_C[i0, i1] }"
+            },
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb8[i0, i1] -> MemRef_tmp_0__phi[] }"
+            }
+         ],
+         "domain" : "{ Stmt_bb8[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
+         "name" : "Stmt_bb8",
+         "schedule" : "{ Stmt_bb8[i0, i1] -> [i0, i1, 0, 0, 0] }"
+      },
+      {
+         "accesses" : [
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0__phi[] }"
+            },
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0[] }"
+            },
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb10[i0, i1, i2] -> MemRef_tmp_0_lcssa__phi[] }"
+            }
+         ],
+         "domain" : "{ Stmt_bb10[i0, i1, i2] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 and 0 <= i2 <= 1024 }",
+         "name" : "Stmt_bb10",
+         "schedule" : "{ Stmt_bb10[i0, i1, i2] -> [i0, i1, 1, i2, 0] }"
+      },
+      {
+         "accesses" : [
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_tmp_0__phi[] }"
+            },
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_A[i0, i2] }"
+            },
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_B[i2, i1] }"
+            },
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb13[i0, i1, i2] -> MemRef_tmp_0[] }"
+            }
+         ],
+         "domain" : "{ Stmt_bb13[i0, i1, i2] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 and 0 <= i2 <= 1023 }",
+         "name" : "Stmt_bb13",
+         "schedule" : "{ Stmt_bb13[i0, i1, i2] -> [i0, i1, 1, i2, 1] }"
+      },
+      {
+         "accesses" : [
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb11[i0, i1] -> MemRef_tmp_0_lcssa__phi[] }"
+            },
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb11[i0, i1] -> MemRef_tmp_0_lcssa[] }"
+            }
+         ],
+         "domain" : "{ Stmt_bb11[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
+         "name" : "Stmt_bb11",
+         "schedule" : "{ Stmt_bb11[i0, i1] -> [i0, i1, 2, 0, 0] }"
+      },
+      {
+         "accesses" : [
+            {
+               "kind" : "write",
+               "relation" : "{ Stmt_bb21[i0, i1] -> MemRef_C[i0, i1] }"
+            },
+            {
+               "kind" : "read",
+               "relation" : "{ Stmt_bb21[i0, i1] -> MemRef_tmp_0_lcssa[] }"
+            }
+         ],
+         "domain" : "{ Stmt_bb21[i0, i1] : 0 <= i0 <= 1023 and 0 <= i1 <= 1023 }",
+         "name" : "Stmt_bb21",
+         "schedule" : "{ Stmt_bb21[i0, i1] -> [i0, i1, 3, 0, 0] }"
+      }
+   ]
+}