diff options
| author | River Riddle <riverriddle@google.com> | 2019-02-06 12:59:50 -0800 |
|---|---|---|
| committer | jpienaar <jpienaar@google.com> | 2019-03-29 16:18:59 -0700 |
| commit | fd2d7c857b9cfecb91346a6ef6dc6bf13b98ae1d (patch) | |
| tree | df2d981ec1b959ceaf168ba36a6114bee029e0d2 /mlir/utils | |
| parent | 888b9fa8a6bc828814dc2df7e57abcc443f6517e (diff) | |
| download | bcm5719-llvm-fd2d7c857b9cfecb91346a6ef6dc6bf13b98ae1d.tar.gz bcm5719-llvm-fd2d7c857b9cfecb91346a6ef6dc6bf13b98ae1d.zip | |
Rename the 'if' operation in the AffineOps dialect to 'affine.if' and namespace
the AffineOps dialect with 'affine'.
PiperOrigin-RevId: 232728977
Diffstat (limited to 'mlir/utils')
| -rw-r--r-- | mlir/utils/emacs/mlir-mode.el | 2 | ||||
| -rw-r--r-- | mlir/utils/vim/mlir.vim | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/mlir/utils/emacs/mlir-mode.el b/mlir/utils/emacs/mlir-mode.el index 16c3f69ca3b..8918890b8be 100644 --- a/mlir/utils/emacs/mlir-mode.el +++ b/mlir/utils/emacs/mlir-mode.el @@ -42,7 +42,7 @@ ;; Keywords `(,(regexp-opt '(;; Toplevel entities - "br" "ceildiv" "func" "cond_br" "else" "extfunc" "false" "floordiv" "affine.for" "if" "mod" "return" "size" "step" "to" "true" "??" ) 'symbols) . font-lock-keyword-face)) + "br" "ceildiv" "func" "cond_br" "else" "extfunc" "false" "floordiv" "affine.for" "affine.if" "mod" "return" "size" "step" "to" "true" "??" ) 'symbols) . font-lock-keyword-face)) "Syntax highlighting for MLIR.") ;; Emacs 23 compatibility. diff --git a/mlir/utils/vim/mlir.vim b/mlir/utils/vim/mlir.vim index 93291a719ae..0e2797f5603 100644 --- a/mlir/utils/vim/mlir.vim +++ b/mlir/utils/vim/mlir.vim @@ -11,7 +11,7 @@ syn keyword mlirType index i1 i2 i4 i8 i13 i16 i32 i64 syn keyword mlirType memref tensor vector syntax keyword mlirKeywords extfunc func to step return -syntax keyword mlirConditional if else +syntax keyword mlirConditional affine.if else syntax keyword mlirCoreOps dim addf addi subf subi mulf muli cmpi select constant affine.apply affine.for call call_indirect extract_element getTensor memref_cast tensor_cast load store alloc dealloc dma_start dma_wait syn match mlirInt "-\=\<\d\+\>" |
