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| author | River Riddle <riverriddle@google.com> | 2019-07-09 10:40:29 -0700 |
|---|---|---|
| committer | A. Unique TensorFlower <gardener@tensorflow.org> | 2019-07-09 10:41:00 -0700 |
| commit | 89bc449cee6ca6b9d4c220a8782ee324fab565e0 (patch) | |
| tree | f6192ea26a525a998137c1d7caff6fdf62ccbe7c /mlir/test/Examples | |
| parent | 4cabebf04d04fdd1db404872b026b5aa4bf58a9e (diff) | |
| download | bcm5719-llvm-89bc449cee6ca6b9d4c220a8782ee324fab565e0.tar.gz bcm5719-llvm-89bc449cee6ca6b9d4c220a8782ee324fab565e0.zip | |
Standardize the value numbering in the AsmPrinter.
Change the AsmPrinter to number values breadth-first so that values in adjacent regions can have the same name. This allows for ModuleOp to contain operations that produce results. This also standardizes the special name of region entry arguments to "arg[0-9+]" now that Functions are also operations.
PiperOrigin-RevId: 257225069
Diffstat (limited to 'mlir/test/Examples')
| -rw-r--r-- | mlir/test/Examples/Linalg/Linalg1.mlir | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/mlir/test/Examples/Linalg/Linalg1.mlir b/mlir/test/Examples/Linalg/Linalg1.mlir index acd10e8882c..f4910f0c220 100644 --- a/mlir/test/Examples/Linalg/Linalg1.mlir +++ b/mlir/test/Examples/Linalg/Linalg1.mlir @@ -36,17 +36,17 @@ func @slice_op(%arg0: memref<?x?xf32>) { } return } -// CHECK-LABEL: func @slice_op(%arg0: memref<?x?xf32>) { -// CHECK: %[[M:.*]] = dim %arg0, 0 : memref<?x?xf32> -// CHECK: %[[N:.*]] = dim %arg0, 1 : memref<?x?xf32> -// CHECK: %[[r1:.*]] = linalg.range %c0:%[[M]]:%c1 : !linalg.range -// CHECK: %[[r2:.*]] = linalg.range %c0:%[[N]]:%c1 : !linalg.range -// CHECK: %[[V:.*]] = linalg.view %arg0[%[[r1]], %[[r2]]] : memref<?x?xf32>, !linalg.range, !linalg.range, !linalg.view<?x?xf32> -// CHECK: affine.for %i0 = 0 to #map1(%0) { -// CHECK: affine.for %i1 = 0 to #map1(%1) { -// CHECK: {{.*}} = linalg.slice %[[V]][%i0] {dim = 1} : !linalg.view<?x?xf32>, index -// CHECK: %[[V2:.*]] = linalg.slice %[[V]][%i1] {dim = 0} : !linalg.view<?x?xf32>, index -// CHECK: {{.*}} = linalg.slice %[[V2]][%i0] {dim = 0} : !linalg.view<?xf32>, index +// CHECK-LABEL: func @slice_op(%{{.*}}: memref<?x?xf32>) { +// CHECK: %[[M:.*]] = dim %{{.*}}, 0 : memref<?x?xf32> +// CHECK: %[[N:.*]] = dim %{{.*}}, 1 : memref<?x?xf32> +// CHECK: %[[r1:.*]] = linalg.range %{{.*}}:%[[M]]:%{{.*}} : !linalg.range +// CHECK: %[[r2:.*]] = linalg.range %{{.*}}:%[[N]]:%{{.*}} : !linalg.range +// CHECK: %[[V:.*]] = linalg.view %{{.*}}[%[[r1]], %[[r2]]] : memref<?x?xf32>, !linalg.range, !linalg.range, !linalg.view<?x?xf32> +// CHECK: affine.for %{{.*}} = 0 to #map1(%{{.*}}) { +// CHECK: affine.for %{{.*}} = 0 to #map1(%{{.*}}) { +// CHECK: {{.*}} = linalg.slice %[[V]][%{{.*}}] {dim = 1} : !linalg.view<?x?xf32>, index +// CHECK: %[[V2:.*]] = linalg.slice %[[V]][%{{.*}}] {dim = 0} : !linalg.view<?x?xf32>, index +// CHECK: {{.*}} = linalg.slice %[[V2]][%{{.*}}] {dim = 0} : !linalg.view<?xf32>, index func @rangeConversion(%arg0: index, %arg1: index, %arg2: index) { %0 = linalg.range %arg0:%arg1:%arg2 : !linalg.range |
